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Searched refs:NUM_WM_RANGES (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Ddcn301_smu.h67 #define NUM_WM_RANGES 4 macro
77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/drivers/gpu/drm/amd/pm/inc/
Dsmu10_driver_if.h61 #define NUM_WM_RANGES 4 macro
70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
Dsmu13_driver_if_yellow_carp.h60 #define NUM_WM_RANGES 4 macro
72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
Dsmu12_driver_if.h61 #define NUM_WM_RANGES 4 macro
73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
Dsmu11_driver_if_vangogh.h60 #define NUM_WM_RANGES 4 macro
72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
Dsmu9_driver_if.h337 #define NUM_WM_RANGES 4 macro
347 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
Dsmu11_driver_if.h688 #define NUM_WM_RANGES 4 macro
698 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
Dsmu11_driver_if_navi10.h1032 #define NUM_WM_RANGES 4 macro
1042 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
Dsmu11_driver_if_sienna_cichlid.h1489 #define NUM_WM_RANGES 4 macro
1506 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_smu.h62 #define NUM_WM_RANGES 4 macro
74 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
231 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr_smu_msg.h62 #define NUM_WM_RANGES 4 macro
79 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
/drivers/gpu/drm/amd/pm/inc/vega12/
Dsmu9_driver_if.h581 #define NUM_WM_RANGES 4 macro
591 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dyellow_carp_ppt.c522 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in yellow_carp_set_watermarks_table()
523 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c1042 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in renoir_set_watermarks_table()
1043 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c1354 for (i = 0; i < NUM_WM_RANGES; i++) in smu10_set_watermarks_for_clocks_ranges()
1357 for (i = 0; i < NUM_WM_RANGES; i++) in smu10_set_watermarks_for_clocks_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1571 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in vangogh_set_watermarks_table()
1572 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in vangogh_set_watermarks_table()
Dnavi10_ppt.c1939 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in navi10_set_watermarks_table()
1940 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in navi10_set_watermarks_table()
Dsienna_cichlid_ppt.c1681 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in sienna_cichlid_set_watermarks_table()
1682 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in sienna_cichlid_set_watermarks_table()