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Searched refs:WatermarkRow (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c421 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
424 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
425 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
427 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn31_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges()
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges()
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn31_build_watermark_ranges()
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
[all …]
Ddcn31_smu.h74 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
231 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c409 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
412 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
415 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in vg_build_watermark_ranges()
417 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in vg_build_watermark_ranges()
420 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in vg_build_watermark_ranges()
423 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in vg_build_watermark_ranges()
428 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
[all …]
Ddcn301_smu.h77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.c737 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
741 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
745 table->WatermarkRow[1][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
749 table->WatermarkRow[1][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
753 table->WatermarkRow[1][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
758 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
762 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
766 table->WatermarkRow[0][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
770 table->WatermarkRow[0][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
774 table->WatermarkRow[0][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
Dsmu_helper.h46 struct watermark_row_generic_t WatermarkRow[2][4]; member
Dsmu10_hwmgr.c1355 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
1358 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c1048 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1050 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
1052 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table()
1054 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in renoir_set_watermarks_table()
1057 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in renoir_set_watermarks_table()
1059 table->WatermarkRow[WM_DCFCLK][i].WmType = in renoir_set_watermarks_table()
1064 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()
1066 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table()
1068 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in renoir_set_watermarks_table()
1070 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in renoir_set_watermarks_table()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dyellow_carp_ppt.c527 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
529 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
531 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
533 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
536 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
541 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
543 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
545 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
547 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
550 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c378 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
379 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
380 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
381 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
382 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i; in dcn3_notify_wm_ranges()
383 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
Ddcn30_clk_mgr_smu_msg.h79 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1576 table->WatermarkRow[WM_DCFCLK][i].MinClock = in vangogh_set_watermarks_table()
1578 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table()
1580 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in vangogh_set_watermarks_table()
1582 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1585 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in vangogh_set_watermarks_table()
1590 table->WatermarkRow[WM_SOCCLK][i].MinClock = in vangogh_set_watermarks_table()
1592 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in vangogh_set_watermarks_table()
1594 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in vangogh_set_watermarks_table()
1596 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1599 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in vangogh_set_watermarks_table()
Dnavi10_ppt.c1944 table->WatermarkRow[WM_DCEFCLK][i].MinClock = in navi10_set_watermarks_table()
1946 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in navi10_set_watermarks_table()
1948 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = in navi10_set_watermarks_table()
1950 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = in navi10_set_watermarks_table()
1953 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = in navi10_set_watermarks_table()
1958 table->WatermarkRow[WM_SOCCLK][i].MinClock = in navi10_set_watermarks_table()
1960 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in navi10_set_watermarks_table()
1962 table->WatermarkRow[WM_SOCCLK][i].MinUclk = in navi10_set_watermarks_table()
1964 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = in navi10_set_watermarks_table()
1967 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in navi10_set_watermarks_table()
Dsienna_cichlid_ppt.c1686 table->WatermarkRow[WM_DCEFCLK][i].MinClock = in sienna_cichlid_set_watermarks_table()
1688 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
1690 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = in sienna_cichlid_set_watermarks_table()
1692 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = in sienna_cichlid_set_watermarks_table()
1695 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = in sienna_cichlid_set_watermarks_table()
1700 table->WatermarkRow[WM_SOCCLK][i].MinClock = in sienna_cichlid_set_watermarks_table()
1702 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
1704 table->WatermarkRow[WM_SOCCLK][i].MinUclk = in sienna_cichlid_set_watermarks_table()
1706 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = in sienna_cichlid_set_watermarks_table()
1709 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in sienna_cichlid_set_watermarks_table()
/drivers/gpu/drm/amd/pm/inc/
Dsmu10_driver_if.h70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu13_driver_if_yellow_carp.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu12_driver_if.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu11_driver_if_vangogh.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu9_driver_if.h347 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu11_driver_if.h698 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES]; member
Dsmu11_driver_if_navi10.h1042 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu11_driver_if_sienna_cichlid.h1506 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/drivers/gpu/drm/amd/pm/inc/vega12/
Dsmu9_driver_if.h591 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES]; member