Searched refs:clock_req (Results 1 – 13 of 13) sorted by relevance
| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 663 struct pp_display_clock_request clock_req; in pp_nv_set_hard_min_dcefclk_by_freq() local
668 clock_req.clock_type = amd_pp_dcef_clock; in pp_nv_set_hard_min_dcefclk_by_freq()
669 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_dcefclk_by_freq()
674 if (pp_funcs->display_clock_voltage_request(pp_handle, &clock_req)) in pp_nv_set_hard_min_dcefclk_by_freq()
687 struct pp_display_clock_request clock_req; in pp_nv_set_hard_min_uclk_by_freq() local
692 clock_req.clock_type = amd_pp_mem_clock; in pp_nv_set_hard_min_uclk_by_freq()
693 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_uclk_by_freq()
698 if (pp_funcs->display_clock_voltage_request(pp_handle, &clock_req)) in pp_nv_set_hard_min_uclk_by_freq()
728 struct pp_display_clock_request clock_req; in pp_nv_set_voltage_by_freq() local
735 clock_req.clock_type = amd_pp_disp_clock; in pp_nv_set_voltage_by_freq()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu10_hwmgr.c | 52 struct pp_display_clock_request *clock_req) in smu10_display_clock_voltage_request() argument
55 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu10_display_clock_voltage_request()
56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu10_display_clock_voltage_request()
192 struct pp_display_clock_request clock_req; in smu10_set_clock_limit() local
195 clock_req.clock_type = amd_pp_dcf_clock; in smu10_set_clock_limit()
196 clock_req.clock_freq_in_khz = clocks.dcefClock * 10; in smu10_set_clock_limit()
198 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), in smu10_set_clock_limit()
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| D | vega12_hwmgr.c | 1543 struct pp_display_clock_request *clock_req) in vega12_display_clock_voltage_request() argument
1547 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request()
1548 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega12_display_clock_voltage_request()
1590 struct pp_display_clock_request clock_req; in vega12_notify_smc_display_config_after_ps_adjustment() local
1604 clock_req.clock_type = amd_pp_dcef_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1605 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; in vega12_notify_smc_display_config_after_ps_adjustment()
1606 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { in vega12_notify_smc_display_config_after_ps_adjustment()
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| D | vega20_hwmgr.c | 2287 struct pp_display_clock_request *clock_req) in vega20_display_clock_voltage_request() argument
2291 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega20_display_clock_voltage_request()
2292 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega20_display_clock_voltage_request()
2343 struct pp_display_clock_request clock_req; in vega20_notify_smc_display_config_after_ps_adjustment() local
2351 clock_req.clock_type = amd_pp_dcef_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
2352 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()
2353 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { in vega20_notify_smc_display_config_after_ps_adjustment()
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| D | vega10_hwmgr.c | 3979 struct pp_display_clock_request *clock_req) in vega10_display_clock_voltage_request() argument
3982 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega10_display_clock_voltage_request()
3983 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega10_display_clock_voltage_request()
4049 struct pp_display_clock_request clock_req; in vega10_notify_smc_display_config_after_ps_adjustment() local
4068 clock_req.clock_type = amd_pp_dcef_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
4069 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; in vega10_notify_smc_display_config_after_ps_adjustment()
4070 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { in vega10_notify_smc_display_config_after_ps_adjustment()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | smu_v13_0.h | 181 *clock_req);
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| D | smu_v11_0.h | 215 *clock_req);
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| D | amdgpu_smu.h | 1041 *clock_req);
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0.c | 1007 *clock_req) in smu_v13_0_display_clock_voltage_request()
1009 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v13_0_display_clock_voltage_request()
1012 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu_v13_0_display_clock_voltage_request()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | smu_v11_0.c | 1087 *clock_req) in smu_v11_0_display_clock_voltage_request()
1089 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request()
1092 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu_v11_0_display_clock_voltage_request()
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| D | navi10_ppt.c | 1892 struct pp_display_clock_request clock_req; in navi10_notify_smc_display_config() local
1900 clock_req.clock_type = amd_pp_dcef_clock; in navi10_notify_smc_display_config()
1901 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_display_config()
1903 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); in navi10_notify_smc_display_config()
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| D | sienna_cichlid_ppt.c | 1634 struct pp_display_clock_request clock_req; in sienna_cichlid_notify_smc_display_config() local
1642 clock_req.clock_type = amd_pp_dcef_clock; in sienna_cichlid_notify_smc_display_config()
1643 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in sienna_cichlid_notify_smc_display_config()
1645 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); in sienna_cichlid_notify_smc_display_config()
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| /drivers/gpu/drm/amd/pm/swsmu/ |
| D | amdgpu_smu.c | 2704 struct pp_display_clock_request *clock_req) in smu_display_clock_voltage_request() argument
2715 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); in smu_display_clock_voltage_request()
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