| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | Makefile | 57 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/dcn2x/dcn2x.o := $(dml_ccflags)
62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
63 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
64 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
65 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
66 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
67 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
68 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1635 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; in dcn31_populate_dml_pipes_from_context()
1642 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1653 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
1654 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
1655 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
1666 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
1668 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
1669 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()
1682 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1691 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1515 if (dc->dml.ip.writeback_max_hscl_taps > 1) { in dcn30_populate_dml_writeback_from_context()
1555 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_populate_dml_writeback_from_context()
1599 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1626 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_set_mcif_arb_params()
1627 …wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 10… in dcn30_set_mcif_arb_params()
1635 …wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] *… in dcn30_set_mcif_arb_params()
1877 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1891 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1899 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn30_internal_validate_bw()
1901 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
[all …]
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| D | dcn30_hwseq.c | 292 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
308 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1038 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
1042 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
1044 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1047 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1048 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1050 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
1051 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
1052 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; in calculate_wm_set_for_vlevel()
1054 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1055 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
[all …]
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
505 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); in dcn_bw_calc_rq_dlg_ttu()
506 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
508 dml, in dcn_bw_calc_rq_dlg_ttu()
1094 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
1095 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; in dcn_validate_bandwidth()
1310 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn_validate_bandwidth()
1312 context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; in dcn_validate_bandwidth()
1751 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; in dcn_bw_sync_calcs_and_dml()
1752 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; in dcn_bw_sync_calcs_and_dml()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 2201 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; in dcn20_populate_dml_pipes_from_context()
2431 …wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) *… in dcn20_set_mcif_arb_params()
2432 …wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipe… in dcn20_set_mcif_arb_params()
2634 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
2689 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
2694 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2837 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2839 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2857 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2876 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1624 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn301_update_bw_bounding_box()
1626 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); in dcn301_update_bw_bounding_box()
1633 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
1637 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
1639 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1642 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1643 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1645 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
1646 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
1647 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; in calculate_wm_set_for_vlevel()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn3_build_wm_range_table()
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table()
139 …able.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_la… in dcn3_build_wm_range_table()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | Makefile | 31 DC_LIBS += dcn10 dml
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| D | dc.h | 668 struct display_mode_lib dml; member
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 1351 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp() local
1353 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
1533 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); in dcn10_resource_construct()
1644 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 1828 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
3401 struct display_mode_lib *dml; in dc_set_power_state() local
3430 dml = kzalloc(sizeof(struct display_mode_lib), in dc_set_power_state()
3433 ASSERT(dml); in dc_set_power_state()
3434 if (!dml) in dc_set_power_state()
3440 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib)); in dc_set_power_state()
3447 dc->current_state->bw_ctx.dml = *dml; in dc_set_power_state()
3449 kfree(dml); in dc_set_power_state()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 1304 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn302_update_bw_bounding_box()
1420 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_update_bw_bounding_box()
1422 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_update_bw_bounding_box()
1623 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 1234 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn303_update_bw_bounding_box()
1362 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_update_bw_bounding_box()
1364 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_update_bw_bounding_box()
1554 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 431 struct display_mode_lib dml; member
|