Home
last modified time | relevance | path

Searched refs:high_water (Results 1 – 19 of 19) sorted by relevance

/drivers/net/ethernet/intel/ixgb/
Dixgb_param.c336 adapter->hw.fc.high_water = RxFCHighThresh[bd]; in ixgb_check_options()
337 ixgb_validate_option(&adapter->hw.fc.high_water, &opt); in ixgb_check_options()
339 adapter->hw.fc.high_water = opt.def; in ixgb_check_options()
386 if (adapter->hw.fc.high_water < (adapter->hw.fc.low_water + 8)) { in ixgb_check_options()
389 adapter->hw.fc.high_water = DEFAULT_FCRTH; in ixgb_check_options()
Dixgb_hw.h614 u32 high_water; /* Flow Control High-water */ member
Dixgb_hw.c691 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); in ixgb_setup_fc()
/drivers/atm/
Dzatm.c213 while (free < zatm_dev->pool_info[pool].high_water) { in refill_pool()
619 zatm_dev->pool_info[i].high_water = HIGH_MARK; in start_rx()
1493 if (!info.high_water) in zatm_ioctl()
1494 info.high_water = zatm_dev-> in zatm_ioctl()
1495 pool_info[pool].high_water; in zatm_ioctl()
1499 if (info.low_water >= info.high_water || in zatm_ioctl()
1505 zatm_dev->pool_info[pool].high_water = in zatm_ioctl()
1506 info.high_water; in zatm_ioctl()
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_82598.c291 hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
293 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
383 hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
385 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_82598()
Dixgbe_dcb_82598.c203 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
Dixgbe_dcb_82599.c235 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82599()
Dixgbe_common.c2142 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2144 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2214 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2217 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
Dixgbe_type.h3294 u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */ member
Dixgbe_main.c5209 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); in ixgbe_pbthresh_setup()
5213 if (hw->fc.low_water[i] > hw->fc.high_water[i]) in ixgbe_pbthresh_setup()
5218 hw->fc.high_water[i] = 0; in ixgbe_pbthresh_setup()
/drivers/net/ethernet/intel/igc/
Digc_hw.h176 u32 high_water; /* Flow control high-water mark */ member
Digc_mac.c101 fcrth = hw->fc.high_water; in igc_set_fc_watermarks()
Digc_main.c99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ in igc_reset()
100 fc->low_water = fc->high_water - 16; in igc_reset()
/drivers/net/ethernet/intel/igb/
De1000_hw.h465 u32 high_water; /* Flow control high-water mark */ member
De1000_mac.c777 fcrth = hw->fc.high_water; in igb_set_fc_watermarks()
Digb_main.c2347 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ in igb_reset()
2348 fc->low_water = fc->high_water - 16; in igb_reset()
/drivers/net/ethernet/intel/e1000e/
Dhw.h660 u32 high_water; /* Flow control high-water mark */ member
Dnetdev.c4042 fc->high_water = 0x2800; in e1000e_reset()
4043 fc->low_water = fc->high_water - 8; in e1000e_reset()
4051 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ in e1000e_reset()
4052 fc->low_water = fc->high_water - 8; in e1000e_reset()
4059 fc->high_water = 0x3500; in e1000e_reset()
4062 fc->high_water = 0x5000; in e1000e_reset()
4079 fc->high_water = 0x05C20; in e1000e_reset()
4086 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; in e1000e_reset()
Dmac.c923 fcrth = hw->fc.high_water; in e1000e_set_fc_watermarks()