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Searched refs:lvds (Results 1 – 25 of 35) sorted by relevance

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/drivers/gpu/drm/rockchip/
Drockchip_lvds.c50 int (*probe)(struct platform_device *pdev, struct rockchip_lvds *lvds);
71 static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset, in rk3288_writel() argument
74 writel_relaxed(val, lvds->regs + offset); in rk3288_writel()
75 if (lvds->output == DISPLAY_OUTPUT_LVDS) in rk3288_writel()
77 writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); in rk3288_writel()
114 struct rockchip_lvds *lvds = connector_to_lvds(connector); in rockchip_lvds_connector_get_modes() local
115 struct drm_panel *panel = lvds->panel; in rockchip_lvds_connector_get_modes()
138 static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) in rk3288_lvds_poweron() argument
143 ret = clk_enable(lvds->pclk); in rk3288_lvds_poweron()
145 DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); in rk3288_lvds_poweron()
[all …]
/drivers/gpu/drm/rcar-du/
Drcar_lvds.c56 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
82 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) in rcar_lvds_write() argument
84 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
91 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq) in rcar_lvds_pll_setup_gen2() argument
104 rcar_lvds_write(lvds, LVDPLLCR, val); in rcar_lvds_pll_setup_gen2()
107 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq) in rcar_lvds_pll_setup_gen3() argument
120 rcar_lvds_write(lvds, LVDPLLCR, val); in rcar_lvds_pll_setup_gen3()
132 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, in rcar_lvds_d3_e3_pll_calc() argument
256 dev_dbg(lvds->dev, in rcar_lvds_d3_e3_pll_calc()
263 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, in __rcar_lvds_pll_setup_d3_e3() argument
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Drcar_du_of.c105 RCAR_DU_OF_DTB(lvds, r8a7790);
106 RCAR_DU_OF_DTB(lvds, r8a7791);
107 RCAR_DU_OF_DTB(lvds, r8a7793);
108 RCAR_DU_OF_DTB(lvds, r8a7795);
109 RCAR_DU_OF_DTB(lvds, r8a7796);
112 RCAR_DU_OF_OVERLAY(lvds, r8a7790),
113 RCAR_DU_OF_OVERLAY(lvds, r8a7791),
114 RCAR_DU_OF_OVERLAY(lvds, r8a7793),
115 RCAR_DU_OF_OVERLAY(lvds, r8a7795),
116 RCAR_DU_OF_OVERLAY(lvds, r8a7796),
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Drcar_du_of_lvds_r8a7790.dts15 lvds@feb90000 {
16 compatible = "renesas,r8a7790-lvds";
36 lvds@feb94000 {
37 compatible = "renesas,r8a7790-lvds";
Drcar_du_of_lvds_r8a7791.dts15 lvds@feb90000 {
16 compatible = "renesas,r8a7791-lvds";
Drcar_du_of_lvds_r8a7793.dts15 lvds@feb90000 {
16 compatible = "renesas,r8a7793-lvds";
Drcar_du_of_lvds_r8a7795.dts15 lvds@feb90000 {
16 compatible = "renesas,r8a7795-lvds";
Drcar_du_of_lvds_r8a7796.dts15 lvds@feb90000 {
16 compatible = "renesas,r8a7796-lvds";
Drcar_du_drv.h91 struct drm_bridge *lvds[RCAR_DU_MAX_LVDS]; member
/drivers/gpu/drm/panel/
Dpanel-lvds.c51 struct panel_lvds *lvds = to_panel_lvds(panel); in panel_lvds_unprepare() local
53 if (lvds->enable_gpio) in panel_lvds_unprepare()
54 gpiod_set_value_cansleep(lvds->enable_gpio, 0); in panel_lvds_unprepare()
56 if (lvds->supply) in panel_lvds_unprepare()
57 regulator_disable(lvds->supply); in panel_lvds_unprepare()
64 struct panel_lvds *lvds = to_panel_lvds(panel); in panel_lvds_prepare() local
66 if (lvds->supply) { in panel_lvds_prepare()
69 err = regulator_enable(lvds->supply); in panel_lvds_prepare()
71 dev_err(lvds->dev, "failed to enable supply: %d\n", in panel_lvds_prepare()
77 if (lvds->enable_gpio) in panel_lvds_prepare()
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/drivers/gpu/drm/sun4i/
Dsun4i_lvds.c44 struct sun4i_lvds *lvds = in sun4i_lvds_get_modes() local
47 return drm_panel_get_modes(lvds->panel, connector); in sun4i_lvds_get_modes()
70 struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(encoder); in sun4i_lvds_encoder_enable() local
74 if (lvds->panel) { in sun4i_lvds_encoder_enable()
75 drm_panel_prepare(lvds->panel); in sun4i_lvds_encoder_enable()
76 drm_panel_enable(lvds->panel); in sun4i_lvds_encoder_enable()
82 struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(encoder); in sun4i_lvds_encoder_disable() local
86 if (lvds->panel) { in sun4i_lvds_encoder_disable()
87 drm_panel_disable(lvds->panel); in sun4i_lvds_encoder_disable()
88 drm_panel_unprepare(lvds->panel); in sun4i_lvds_encoder_disable()
[all …]
/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser.c1215 ATOM_LVDS_INFO_V12 *lvds; in get_embedded_panel_info_v1_2() local
1223 lvds = in get_embedded_panel_info_v1_2()
1226 if (!lvds) in get_embedded_panel_info_v1_2()
1229 if (1 != lvds->sHeader.ucTableFormatRevision in get_embedded_panel_info_v1_2()
1230 || 2 > lvds->sHeader.ucTableContentRevision) in get_embedded_panel_info_v1_2()
1237 le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10; in get_embedded_panel_info_v1_2()
1240 le16_to_cpu(lvds->sLCDTiming.usHActive); in get_embedded_panel_info_v1_2()
1246 le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time); in get_embedded_panel_info_v1_2()
1249 le16_to_cpu(lvds->sLCDTiming.usVActive); in get_embedded_panel_info_v1_2()
1255 le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time); in get_embedded_panel_info_v1_2()
[all …]
Dbios_parser2.c1111 struct lcd_info_v2_1 *lvds; in get_embedded_panel_info_v2_1() local
1119 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); in get_embedded_panel_info_v2_1()
1121 if (!lvds) in get_embedded_panel_info_v2_1()
1125 if (!((lvds->table_header.format_revision == 2) in get_embedded_panel_info_v2_1()
1126 && (lvds->table_header.content_revision >= 1))) in get_embedded_panel_info_v2_1()
1132 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()
1134 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); in get_embedded_panel_info_v2_1()
1140 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); in get_embedded_panel_info_v2_1()
1142 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); in get_embedded_panel_info_v2_1()
1148 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); in get_embedded_panel_info_v2_1()
[all …]
/drivers/gpu/drm/radeon/
Dradeon_combios.c1103 struct radeon_encoder_lvds *lvds = NULL; in radeon_legacy_get_lvds_info_from_regs() local
1108 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); in radeon_legacy_get_lvds_info_from_regs()
1110 if (!lvds) in radeon_legacy_get_lvds_info_from_regs()
1117 lvds->panel_pwr_delay = 200; in radeon_legacy_get_lvds_info_from_regs()
1118 lvds->panel_vcc_delay = 2000; in radeon_legacy_get_lvds_info_from_regs()
1120 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()
1121 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()
1122 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()
1125 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()
1129 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()
[all …]
Dradeon_legacy_encoders.c70 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local
71 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()
72 if (lvds->bl_dev) in radeon_legacy_lvds_update()
73 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()
75 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local
76 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()
77 if (lvds->bl_dev) in radeon_legacy_lvds_update()
78 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()
151 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_dpms() local
152 lvds->dpms_mode = mode; in radeon_legacy_lvds_dpms()
[all …]
Dradeon_atombios.c1624 struct radeon_encoder_atom_dig *lvds = NULL; in radeon_atombios_get_lvds_info() local
1631 lvds = in radeon_atombios_get_lvds_info()
1634 if (!lvds) in radeon_atombios_get_lvds_info()
1637 lvds->native_mode.clock = in radeon_atombios_get_lvds_info()
1639 lvds->native_mode.hdisplay = in radeon_atombios_get_lvds_info()
1641 lvds->native_mode.vdisplay = in radeon_atombios_get_lvds_info()
1643 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()
1645 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()
1647 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in radeon_atombios_get_lvds_info()
1649 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in radeon_atombios_get_lvds_info()
[all …]
Dradeon_legacy_crtc.c799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; in radeon_set_pll() local
800 if (lvds) { in radeon_set_pll()
801 if (lvds->use_bios_dividers) { in radeon_set_pll()
802 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()
803 pll_fb_post_div = (lvds->panel_fb_divider | in radeon_set_pll()
804 (lvds->panel_post_divider << 16)); in radeon_set_pll()
/drivers/gpu/drm/amd/amdgpu/
Datombios_encoders.c1999 struct amdgpu_encoder_atom_dig *lvds = NULL; in amdgpu_atombios_encoder_get_lcd_info() local
2006 lvds = in amdgpu_atombios_encoder_get_lcd_info()
2009 if (!lvds) in amdgpu_atombios_encoder_get_lcd_info()
2012 lvds->native_mode.clock = in amdgpu_atombios_encoder_get_lcd_info()
2014 lvds->native_mode.hdisplay = in amdgpu_atombios_encoder_get_lcd_info()
2016 lvds->native_mode.vdisplay = in amdgpu_atombios_encoder_get_lcd_info()
2018 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()
2020 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()
2022 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in amdgpu_atombios_encoder_get_lcd_info()
2024 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()
[all …]
/drivers/gpu/drm/gma500/
Dpsb_intel_display.c224 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set() local
226 lvds &= ~LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
228 lvds |= LVDS_PIPEB_SELECT; in psb_intel_crtc_mode_set()
230 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; in psb_intel_crtc_mode_set()
235 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in psb_intel_crtc_mode_set()
237 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in psb_intel_crtc_mode_set()
244 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
Dcdv_intel_lvds.c490 u32 lvds; in cdv_intel_lvds_init() local
614 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
615 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in cdv_intel_lvds_init()
618 if (crtc && (lvds & LVDS_PORT_EN)) { in cdv_intel_lvds_init()
Dpsb_intel_lvds.c645 u32 lvds; in psb_intel_lvds_init() local
761 lvds = REG_READ(LVDS); in psb_intel_lvds_init()
762 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; in psb_intel_lvds_init()
765 if (crtc && (lvds & LVDS_PORT_EN)) { in psb_intel_lvds_init()
Dcdv_intel_display.c729 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set() local
731 lvds |= in cdv_intel_crtc_mode_set()
739 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; in cdv_intel_crtc_mode_set()
741 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); in cdv_intel_crtc_mode_set()
748 REG_WRITE(LVDS, lvds); in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/display/
Dintel_lvds.c838 u32 lvds; in intel_lvds_init() local
860 lvds = intel_de_read(dev_priv, lvds_reg); in intel_lvds_init()
863 if ((lvds & LVDS_DETECTED) == 0) in intel_lvds_init()
869 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()
940 lvds_encoder->init_lvds_val = lvds; in intel_lvds_init()
1009 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; in intel_lvds_init()
/drivers/gpu/drm/nouveau/dispnv50/
Ddisp.c1740 struct nv50_disp_sor_lvds_script_v0 lvds; in nv50_sor_atomic_enable() member
1741 } lvds = { in nv50_sor_atomic_enable() local
1793 lvds.lvds.script |= 0x0100; in nv50_sor_atomic_enable()
1795 lvds.lvds.script |= 0x0200; in nv50_sor_atomic_enable()
1799 lvds.lvds.script |= 0x0100; in nv50_sor_atomic_enable()
1802 lvds.lvds.script |= 0x0100; in nv50_sor_atomic_enable()
1805 if (lvds.lvds.script & 0x0100) { in nv50_sor_atomic_enable()
1807 lvds.lvds.script |= 0x0200; in nv50_sor_atomic_enable()
1810 lvds.lvds.script |= 0x0200; in nv50_sor_atomic_enable()
1814 lvds.lvds.script |= 0x0200; in nv50_sor_atomic_enable()
[all …]
/drivers/gpu/drm/bridge/
DMakefile10 obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o

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