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Searched refs:phy_write (Results 1 – 25 of 77) sorted by relevance

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/drivers/net/phy/
Dvitesse.c99 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
108 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
134 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
136 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
150 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
153 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
156 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
157 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
159 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
[all …]
Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
60 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
61 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
73 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
92 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7); in ns_handle_interrupt()
108 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
[all …]
Dbcm7xxx.c80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
356 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
Dmeson-gxl.c59 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
62 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
65 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
68 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
73 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
85 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
109 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
113 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
215 ret = phy_write(phydev, INTSRC_MASK, INT_SOURCES); in meson_gxl_config_intr()
217 ret = phy_write(phydev, INTSRC_MASK, 0); in meson_gxl_config_intr()
Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
358 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
362 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
364 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */ in lan88xx_link_change_notify()
[all …]
Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
159 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
340 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
Dmicrochip_t1.c62 rc = phy_write(phydev, offset, val); in access_ereg()
70 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); in access_ereg()
79 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg); in access_ereg()
189 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, 0x7FFF); in lan87xx_phy_config_intr()
192 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); in lan87xx_phy_config_intr()
194 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val); in lan87xx_phy_config_intr()
Dbcm-phy-lib.c109 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK | in bcm54xx_auxctl_read()
117 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
127 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
134 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
151 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
158 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
196 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
199 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
242 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); in bcm_phy_read_shadow()
250 return phy_write(phydev, MII_BCM54XX_SHD, in bcm_phy_write_shadow()
[all …]
Dbcm63xx.c34 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
37 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
60 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
69 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
Dcicada.c67 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
73 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
95 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
98 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
Dsmsc.c67 rc = phy_write(phydev, MII_LAN83C185_IM, in smsc_phy_config_intr()
70 rc = phy_write(phydev, MII_LAN83C185_IM, 0); in smsc_phy_config_intr()
112 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_init()
132 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); in smsc_phy_reset()
172 phy_write(phydev, SPECIAL_CTRL_STS, rc); in lan87xx_config_aneg()
191 phy_write(phydev, PHY_EDPD_CONFIG, rc); in lan95xx_config_aneg_ext()
221 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
241 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
Dlxt.c88 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
90 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
129 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
152 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
154 err = phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
292 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
Dat803x.c213 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_write()
217 return phy_write(phydev, AT803X_DEBUG_DATA, data); in at803x_debug_reg_write()
224 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
245 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
317 phy_write(phydev, MII_BMCR, context->bmcr); in at803x_context_restore()
318 phy_write(phydev, MII_ADVERTISE, context->advertise); in at803x_context_restore()
319 phy_write(phydev, MII_CTRL1000, context->control1000); in at803x_context_restore()
320 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); in at803x_context_restore()
321 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); in at803x_context_restore()
322 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); in at803x_context_restore()
[all …]
Ddp83869.c208 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
210 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
336 return phy_write(phydev, MII_DP83869_MICR, val_micr); in dp83869_set_wol()
621 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); in dp83869_configure_rgmii()
699 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); in dp83869_configure_mode()
709 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
714 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); in dp83869_configure_mode()
736 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
747 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
753 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
[all …]
Drealtek.c184 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
187 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
206 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
209 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
315 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
316 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
318 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
319 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
477 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
484 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
[all …]
Dbroadcom.c80 phy_write(phydev, MII_CTRL1000, val); in bcm54210e_config_init()
326 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
334 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
556 return phy_write(phydev, reg, val | set); in brcm_phy_setbits()
564 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
599 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
610 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); in brcm_fet_config_init()
624 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); in brcm_fet_config_init()
642 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); in brcm_fet_config_init()
675 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
[all …]
Dqsemi.c71 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
110 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
113 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
Dste10Xp.c40 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
72 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK); in ste10Xp_config_intr()
74 err = phy_write(phydev, MII_XIE, 0); in ste10Xp_config_intr()
Dbcm-cygnus.c25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
55 rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02); in bcm_cygnus_afe_config()
85 rc = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_cygnus_config_init()
93 rc = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm_cygnus_config_init()
Ddp83848.c77 ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK); in dp83848_config_intr()
81 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
84 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
/drivers/net/ethernet/realtek/
Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
447 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
448 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
450 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
467 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
485 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
489 phy_write(phydev, 0x0d, val | set[i]); in rtl8168d_1_hw_phy_config()
[all …]
/drivers/net/ethernet/ibm/emac/
Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c110 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
292 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
293 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
294 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
295 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
296 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
297 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
298 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
314 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
315 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]

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