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Searched refs:pp_smu_wm_range_sets (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h88 struct pp_smu_wm_range_sets { struct
113 struct pp_smu_wm_range_sets *ranges); argument
218 struct pp_smu_wm_range_sets *ranges);
280 struct pp_smu_wm_range_sets *ranges);
299 struct pp_smu_wm_range_sets *ranges);
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h281 struct pp_smu_wm_range_sets ranges;
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c493 struct pp_smu_wm_range_sets *ranges) in pp_rv_set_wm_ranges()
608 struct pp_smu_wm_range_sets *ranges) in pp_nv_set_wm_ranges()
811 struct pp_smu_wm_range_sets *ranges) in pp_rn_set_wm_ranges()
/drivers/gpu/drm/amd/include/
Dkgd_pp_interface.h289 struct pp_smu_wm_range_sets;
389 struct pp_smu_wm_range_sets *ranges);
/drivers/gpu/drm/amd/pm/inc/
Damdgpu_smu.h742 struct pp_smu_wm_range_sets *clock_ranges);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c459 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ra… in build_watermark_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dyellow_carp_ppt.c512 struct pp_smu_wm_range_sets *clock_ranges) in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c1035 struct pp_smu_wm_range_sets *clock_ranges) in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c1535 struct pp_smu_wm_range_sets ranges = {0}; in set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1561 struct pp_smu_wm_range_sets *clock_ranges) in vangogh_set_watermarks_table()
Dnavi10_ppt.c1932 struct pp_smu_wm_range_sets *clock_ranges) in navi10_set_watermarks_table()
Dsienna_cichlid_ppt.c1674 struct pp_smu_wm_range_sets *clock_ranges) in sienna_cichlid_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c1549 struct pp_smu_wm_range_sets ranges = {0}; in dcn_bw_notify_pplib_of_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c2051 struct pp_smu_wm_range_sets *clock_ranges) in smu_set_watermarks_for_clock_ranges()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c3872 struct pp_smu_wm_range_sets ranges = {0}; in dcn20_resource_construct()