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Searched refs:reader_wm_sets (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c470 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
471 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
473 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges()
474 …ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MA… in build_watermark_ranges()
477 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { in build_watermark_ranges()
479 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; in build_watermark_ranges()
482 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
484 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
488 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges()
489 …ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MA… in build_watermark_ranges()
[all …]
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c1574 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1575 ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1576 ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1577 ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1578 ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1586 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1587 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300; in dcn_bw_notify_pplib_of_wm_ranges()
1588 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()
1589 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800; in dcn_bw_notify_pplib_of_wm_ranges()
1590 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()
[all …]
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c508 if (ranges->reader_wm_sets[i].wm_inst > 3) in pp_rv_set_wm_ranges()
512 ranges->reader_wm_sets[i].wm_inst; in pp_rv_set_wm_ranges()
514 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
516 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
518 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
520 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c1541 ranges.reader_wm_sets[0].wm_inst = 0; in set_wm_ranges()
1542 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1543 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1544 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1545 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1550 ranges.reader_wm_sets[i].wm_inst = i; in set_wm_ranges()
1551 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1552 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1553 …ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_m… in set_wm_ranges()
1554 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in set_wm_ranges()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c1049 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in renoir_set_watermarks_table()
1051 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in renoir_set_watermarks_table()
1053 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()
1055 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in renoir_set_watermarks_table()
1058 clock_ranges->reader_wm_sets[i].wm_inst; in renoir_set_watermarks_table()
1060 clock_ranges->reader_wm_sets[i].wm_type; in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dyellow_carp_ppt.c528 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in yellow_carp_set_watermarks_table()
530 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in yellow_carp_set_watermarks_table()
532 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()
534 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in yellow_carp_set_watermarks_table()
537 clock_ranges->reader_wm_sets[i].wm_inst; in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h90 struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS]; member
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c3878 ranges.reader_wm_sets[0].wm_inst = i; in dcn20_resource_construct()
3879 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
3880 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
3881 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
3882 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
3887 ranges.reader_wm_sets[i].wm_inst = i; in dcn20_resource_construct()
3888 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
3889 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
3890 …ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_m… in dcn20_resource_construct()
3891 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in dcn20_resource_construct()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1577 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in vangogh_set_watermarks_table()
1579 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in vangogh_set_watermarks_table()
1581 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()
1583 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in vangogh_set_watermarks_table()
1586 clock_ranges->reader_wm_sets[i].wm_inst; in vangogh_set_watermarks_table()
Dnavi10_ppt.c1945 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in navi10_set_watermarks_table()
1947 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in navi10_set_watermarks_table()
1949 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()
1951 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in navi10_set_watermarks_table()
1954 clock_ranges->reader_wm_sets[i].wm_inst; in navi10_set_watermarks_table()
Dsienna_cichlid_ppt.c1687 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1689 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1691 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1693 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1696 clock_ranges->reader_wm_sets[i].wm_inst; in sienna_cichlid_set_watermarks_table()