/drivers/clk/meson/ |
D | sclk-div.c | 31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) in sclk_div_maxval() argument 33 return (1 << sclk->div.width) - 1; in sclk_div_maxval() 36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) in sclk_div_maxdiv() argument 38 return sclk_div_maxval(sclk) + 1; in sclk_div_maxdiv() 51 struct meson_sclk_div_data *sclk) in sclk_div_bestdiv() argument 61 maxdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv() 92 bestdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv() 103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_round_rate() local 106 div = sclk_div_bestdiv(hw, rate, prate, sclk); in sclk_div_round_rate() 112 struct meson_sclk_div_data *sclk) in sclk_apply_ratio() argument [all …]
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/drivers/clk/hisilicon/ |
D | clkgate-separated.c | 34 struct clkgate_separated *sclk; in clkgate_separated_enable() local 38 sclk = container_of(hw, struct clkgate_separated, hw); in clkgate_separated_enable() 39 if (sclk->lock) in clkgate_separated_enable() 40 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable() 41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable() 42 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable() 43 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable() 44 if (sclk->lock) in clkgate_separated_enable() 45 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable() 51 struct clkgate_separated *sclk; in clkgate_separated_disable() local [all …]
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/drivers/clk/ralink/ |
D | clk-mt7621.c | 131 struct mt7621_gate *sclk) in mt7621_gate_ops_init() argument 136 .parent_names = &sclk->parent_name, in mt7621_gate_ops_init() 138 .name = sclk->name, in mt7621_gate_ops_init() 141 sclk->hw.init = &init; in mt7621_gate_ops_init() 142 return devm_clk_hw_register(dev, &sclk->hw); in mt7621_gate_ops_init() 150 struct mt7621_gate *sclk; in mt7621_register_gates() local 154 sclk = &mt7621_gates[i]; in mt7621_register_gates() 155 sclk->priv = priv; in mt7621_register_gates() 156 ret = mt7621_gate_ops_init(dev, sclk); in mt7621_register_gates() 158 dev_err(dev, "Couldn't register clock %s\n", sclk->name); in mt7621_register_gates() [all …]
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/drivers/clk/ |
D | clk-scmi.c | 105 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) in scmi_clk_ops_init() argument 114 .name = sclk->info->name, in scmi_clk_ops_init() 117 sclk->hw.init = &init; in scmi_clk_ops_init() 118 ret = devm_clk_hw_register(dev, &sclk->hw); in scmi_clk_ops_init() 122 if (sclk->info->rate_discrete) { in scmi_clk_ops_init() 123 int num_rates = sclk->info->list.num_rates; in scmi_clk_ops_init() 128 min_rate = sclk->info->list.rates[0]; in scmi_clk_ops_init() 129 max_rate = sclk->info->list.rates[num_rates - 1]; in scmi_clk_ops_init() 131 min_rate = sclk->info->range.min_rate; in scmi_clk_ops_init() 132 max_rate = sclk->info->range.max_rate; in scmi_clk_ops_init() [all …]
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D | clk-scpi.c | 140 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument 150 sclk->hw.init = &init; in scpi_clk_ops_init() 151 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init() 154 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init() 155 if (IS_ERR(sclk->info)) in scpi_clk_ops_init() 156 return PTR_ERR(sclk->info); in scpi_clk_ops_init() 158 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init() 164 ret = devm_clk_hw_register(dev, &sclk->hw); in scpi_clk_ops_init() 166 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init() 178 struct scpi_clk *sclk; in scpi_of_clk_src_get() local [all …]
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D | clk-nomadik.c | 302 struct clk_src *sclk = to_src(hw); in src_clk_enable() local 303 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; in src_clk_enable() 304 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_enable() 306 writel(sclk->clkbit, src_base + enreg); in src_clk_enable() 308 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable() 315 struct clk_src *sclk = to_src(hw); in src_clk_disable() local 316 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; in src_clk_disable() 317 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_disable() 319 writel(sclk->clkbit, src_base + disreg); in src_clk_disable() 321 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable() [all …]
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/drivers/clk/microchip/ |
D | clk-core.c | 774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local 777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; in sclk_get_rate() 792 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local 799 spin_lock_irqsave(&sclk->core->reg_lock, flags); in sclk_set_rate() 802 v = readl(sclk->slew_reg); in sclk_set_rate() 808 writel(v, sclk->slew_reg); in sclk_set_rate() 811 err = readl_poll_timeout_atomic(sclk->slew_reg, v, in sclk_set_rate() 814 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); in sclk_set_rate() 821 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local 824 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent() [all …]
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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
D | gk104.c | 68 u32 sclk; in read_pll() local 77 sclk = device->crystal; in read_pll() 81 sclk = read_pll(clk, 0x132020); in read_pll() 85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll() 92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll() 101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll() 102 return sclk / (M * P); in read_pll() 121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local 123 return (sclk * 2) / sdiv; in read_div() 149 u32 sclk, sdiv; in read_clk() local [all …]
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D | gf100.c | 67 u32 sclk; in read_pll() local 75 sclk = device->crystal; in read_pll() 79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll() 82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll() 88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll() 94 return sclk * N / M / P; in read_pll() 102 u32 sclk, sctl, sdiv = 2; in read_div() local 112 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() 126 return (sclk * 2) / sdiv; in read_div() 138 u32 sclk, sdiv; in read_clk() local [all …]
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D | gt215.c | 64 u32 sctl, sdiv, sclk; in read_clk() local 99 sclk = read_vco(clk, idx); in read_clk() 101 return (sclk * 2) / sdiv; in read_clk() 112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local 128 sclk = read_clk(clk, 0x00 + idx, false); in read_pll() 131 sclk = read_clk(clk, 0x10 + idx, false); in read_pll() 139 return sclk * N / MP; in read_pll() 191 u32 oclk, sclk, sdiv; in gt215_clk_info() local 207 sclk = read_vco(clk, idx); in gt215_clk_info() 208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info() [all …]
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/drivers/gpu/drm/radeon/ |
D | rv730_dpm.c | 39 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument 106 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value() 107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value() 108 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value() 109 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value() 110 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value() 111 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value() 302 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state() 303 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state() 304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state() [all …]
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D | btc_dpm.c | 1242 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument 1246 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks() 1252 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks() 1259 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks() 1261 if (*sclk < max_sclk) in btc_skip_blacklist_clocks() 1262 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks() 1272 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations() 1275 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations() 1278 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations() 1279 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations() [all …]
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D | rv770_dpm.c | 273 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t() 274 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t() 275 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t() 276 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t() 281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t() 283 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t() 284 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t() 487 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument 557 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value() 558 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value() [all …]
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D | trinity_dpm.c | 540 u32 index, u32 sclk) in trinity_set_divider_value() argument 548 sclk, false, ÷rs); in trinity_set_divider_value() 558 sclk/2, false, ÷rs); in trinity_set_divider_value() 678 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level() 925 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock() 926 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock() 939 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock() 940 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock() 1290 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument 1292 if (sclk < 20000) in trinity_calculate_vce_wm() [all …]
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D | kv_dpm.c | 377 u32 index, u32 sclk) in kv_set_divider_value() argument 384 sclk, false, ÷rs); in kv_set_divider_value() 389 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value() 566 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state() 580 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state() 1537 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range() 1545 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range() 1551 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range() 1552 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range() 1562 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range() [all …]
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D | rv740_dpm.c | 120 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument 175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value() 176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value() 177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value() 178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value() 179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value() 180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value() 385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state() 386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state() 387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state() [all …]
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D | ni_dpm.c | 810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules() 811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules() 829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules() 830 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules() 834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules() 835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules() 864 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules() 865 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules() 874 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules() 1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); in ni_populate_memory_timing_parameters() [all …]
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D | sumo_dpm.c | 347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp() 350 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp() 411 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at() 421 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at() 555 pl->sclk, false, ÷rs); in sumo_program_power_level() 671 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state() 790 pi->acpi_pl.sclk, in sumo_program_acpi_power_level() 844 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock() 845 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock() 862 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock() [all …]
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/drivers/tty/serial/8250/ |
D | 8250_em.c | 24 struct clk *sclk; member 100 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in serial8250_em_probe() 101 if (IS_ERR(priv->sclk)) { in serial8250_em_probe() 103 return PTR_ERR(priv->sclk); in serial8250_em_probe() 114 clk_prepare_enable(priv->sclk); in serial8250_em_probe() 115 up.port.uartclk = clk_get_rate(priv->sclk); in serial8250_em_probe() 126 clk_disable_unprepare(priv->sclk); in serial8250_em_probe() 140 clk_disable_unprepare(priv->sclk); in serial8250_em_remove()
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/drivers/power/reset/ |
D | at91-poweroff.c | 55 struct clk *sclk; member 164 at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe() 165 if (IS_ERR(at91_shdwc.sclk)) in at91_poweroff_probe() 166 return PTR_ERR(at91_shdwc.sclk); in at91_poweroff_probe() 168 ret = clk_prepare_enable(at91_shdwc.sclk); in at91_poweroff_probe() 203 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_probe() 215 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_remove()
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D | at91-reset.c | 56 struct clk *sclk; member 220 reset->sclk = devm_clk_get(&pdev->dev, NULL); in at91_reset_probe() 221 if (IS_ERR(reset->sclk)) in at91_reset_probe() 222 return PTR_ERR(reset->sclk); in at91_reset_probe() 224 ret = clk_prepare_enable(reset->sclk); in at91_reset_probe() 241 clk_disable_unprepare(reset->sclk); in at91_reset_probe() 255 clk_disable_unprepare(reset->sclk); in at91_reset_remove()
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/drivers/media/dvb-frontends/ |
D | cx24110.c | 544 s32 afc; unsigned sclk; in cx24110_get_frontend() local 548 sclk = cx24110_readreg (state, 0x07) & 0x03; in cx24110_get_frontend() 551 if (sclk==0) sclk=90999000L/2L; in cx24110_get_frontend() 552 else if (sclk==1) sclk=60666000L; in cx24110_get_frontend() 553 else if (sclk==2) sclk=80888000L; in cx24110_get_frontend() 554 else sclk=90999000L; in cx24110_get_frontend() 555 sclk>>=8; in cx24110_get_frontend() 556 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ in cx24110_get_frontend() 557 ((sclk*cx24110_readreg (state, 0x45))>>8)+ in cx24110_get_frontend() 558 ((sclk*cx24110_readreg (state, 0x46))>>16); in cx24110_get_frontend()
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/drivers/clocksource/ |
D | timer-atmel-st.c | 185 struct clk *sclk; in atmel_st_timer_init() local 216 sclk = of_clk_get(node, 0); in atmel_st_timer_init() 217 if (IS_ERR(sclk)) { in atmel_st_timer_init() 219 return PTR_ERR(sclk); in atmel_st_timer_init() 222 ret = clk_prepare_enable(sclk); in atmel_st_timer_init() 228 sclk_rate = clk_get_rate(sclk); in atmel_st_timer_init()
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/drivers/gpu/drm/amd/pm/powerplay/ |
D | kv_dpm.c | 662 u32 index, u32 sclk) in kv_set_divider_value() argument 669 sclk, false, ÷rs); in kv_set_divider_value() 674 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value() 807 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state() 821 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state() 1768 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range() 1776 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range() 1782 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range() 1783 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range() 1793 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range() [all …]
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D | si_dpm.c | 1831 SISLANDS_SMC_SCLK_VALUE *sclk); 2402 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values() 2403 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values() 2421 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values() 2422 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values() 2496 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values() 2934 u32 sclk = 0; in si_init_smc_spll_table() local 2947 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); in si_init_smc_spll_table() 2979 sclk += 512; in si_init_smc_spll_table() 3163 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock() [all …]
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