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Searched refs:vic (Results 1 – 25 of 29) sorted by relevance

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/drivers/gpu/drm/tegra/
Dvic.c31 struct vic { struct
45 static inline struct vic *to_vic(struct tegra_drm_client *client) in to_vic() argument
47 return container_of(client, struct vic, client); in to_vic()
50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset) in vic_writel() argument
52 writel(value, vic->regs + offset); in vic_writel()
55 static int vic_boot(struct vic *vic) in vic_boot() argument
58 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); in vic_boot()
65 if (vic->config->supports_sid && spec) { in vic_boot()
70 vic_writel(vic, value, VIC_TFBIF_TRANSCFG); in vic_boot()
85 vic_writel(vic, value, VIC_THI_STREAMID0); in vic_boot()
[all …]
DMakefile26 vic.o
/drivers/irqchip/
Dirq-aspeed-vic.c58 static void vic_init_hw(struct aspeed_vic *vic) in vic_init_hw() argument
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
71 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
72 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
78 sense = readl(vic->base + AVIC_INT_SENSE); in vic_init_hw()
79 vic->edge_sources[0] = ~sense; in vic_init_hw()
80 sense = readl(vic->base + AVIC_INT_SENSE + 4); in vic_init_hw()
[all …]
Dirq-vic.c102 static void resume_one_vic(struct vic_device *vic) in resume_one_vic() argument
104 void __iomem *base = vic->base; in resume_one_vic()
111 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
112 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
115 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
116 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); in resume_one_vic()
120 writel(vic->soft_int, base + VIC_INT_SOFT); in resume_one_vic()
121 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); in resume_one_vic()
132 static void suspend_one_vic(struct vic_device *vic) in suspend_one_vic() argument
134 void __iomem *base = vic->base; in suspend_one_vic()
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DMakefile41 obj-$(CONFIG_ARM_VIC) += irq-vic.o
88 obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
/drivers/gpu/drm/
Ddrm_edid.c3302 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) in cea_mode_for_vic() argument
3307 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) in cea_mode_for_vic()
3308 return &edid_cea_modes_1[vic - 1]; in cea_mode_for_vic()
3309 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) in cea_mode_for_vic()
3310 return &edid_cea_modes_193[vic - 193]; in cea_mode_for_vic()
3319 static u8 cea_next_vic(u8 vic) in cea_next_vic() argument
3321 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) in cea_next_vic()
3322 vic = 193; in cea_next_vic()
3323 return vic; in cea_next_vic()
3352 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) in cea_mode_alternate_timings() argument
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Ddrm_dp_helper.c1015 u8 vic; in drm_dp_downstream_mode() local
1027 vic = 6; in drm_dp_downstream_mode()
1030 vic = 21; in drm_dp_downstream_mode()
1033 vic = 5; in drm_dp_downstream_mode()
1036 vic = 20; in drm_dp_downstream_mode()
1039 vic = 4; in drm_dp_downstream_mode()
1042 vic = 19; in drm_dp_downstream_mode()
1047 return drm_display_mode_from_cea_vic(dev, vic); in drm_dp_downstream_mode()
Ddrm_modes.c2034 u8 vic = drm_match_cea_mode(mode); in drm_mode_is_420_only() local
2036 return test_bit(vic, display->hdmi.y420_vdb_modes); in drm_mode_is_420_only()
2054 u8 vic = drm_match_cea_mode(mode); in drm_mode_is_420_also() local
2056 return test_bit(vic, display->hdmi.y420_cmdb_modes); in drm_mode_is_420_also()
/drivers/gpu/drm/meson/
Dmeson_encoder_hdmi.c70 int vic = drm_match_cea_mode(mode); in meson_encoder_hdmi_set_vclk() local
85 if (!vic) { in meson_encoder_hdmi_set_vclk()
99 if (meson_venc_hdmi_venc_repeat(vic) || in meson_encoder_hdmi_set_vclk()
127 int vic = drm_match_cea_mode(mode); in meson_encoder_hdmi_mode_valid() local
140 if (!vic) { in meson_encoder_hdmi_mode_valid()
147 } else if (!meson_venc_hdmi_supported_vic(vic)) in meson_encoder_hdmi_mode_valid()
169 if (meson_venc_hdmi_venc_repeat(vic) || in meson_encoder_hdmi_mode_valid()
198 int vic; in meson_encoder_hdmi_atomic_enable() local
214 vic = drm_match_cea_mode(mode); in meson_encoder_hdmi_atomic_enable()
216 dev_dbg(priv->dev, "\"%s\" vic %d\n", mode->name, vic); in meson_encoder_hdmi_atomic_enable()
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Dmeson_venc.c818 unsigned int vic; member
879 bool meson_venc_hdmi_supported_vic(int vic) in meson_venc_hdmi_supported_vic() argument
883 while (vmode->vic && vmode->mode) { in meson_venc_hdmi_supported_vic()
884 if (vmode->vic == vic) in meson_venc_hdmi_supported_vic()
918 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) in meson_venc_hdmi_get_vic_vmode() argument
922 while (vmode->vic && vmode->mode) { in meson_venc_hdmi_get_vic_vmode()
923 if (vmode->vic == vic) in meson_venc_hdmi_get_vic_vmode()
931 bool meson_venc_hdmi_venc_repeat(int vic) in meson_venc_hdmi_venc_repeat() argument
934 if (vic == 6 || vic == 7 || /* 480i */ in meson_venc_hdmi_venc_repeat()
935 vic == 21 || vic == 22 || /* 576i */ in meson_venc_hdmi_venc_repeat()
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Dmeson_venc.h53 bool meson_venc_hdmi_supported_vic(int vic);
54 bool meson_venc_hdmi_venc_repeat(int vic);
62 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
/drivers/gpu/drm/rockchip/
Drk3066_hdmi.c24 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ member
222 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) in rk3066_hdmi_config_video_timing()
320 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); in rk3066_hdmi_setup()
323 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || in rk3066_hdmi_setup()
324 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || in rk3066_hdmi_setup()
325 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || in rk3066_hdmi_setup()
326 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) in rk3066_hdmi_setup()
488 u32 vic = drm_match_cea_mode(mode); in rk3066_hdmi_connector_mode_valid() local
490 if (vic > 1) in rk3066_hdmi_connector_mode_valid()
Dinno_hdmi.c32 int vic; member
436 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); in inno_hdmi_setup()
441 if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) || in inno_hdmi_setup()
442 (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) || in inno_hdmi_setup()
443 (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) || in inno_hdmi_setup()
444 (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18)) in inno_hdmi_setup()
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1535 int vic; in analogix_dp_bridge_mode_set() local
1543 vic = drm_match_cea_mode(mode); in analogix_dp_bridge_mode_set()
1544 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || in analogix_dp_bridge_mode_set()
1545 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { in analogix_dp_bridge_mode_set()
1548 } else if (vic) { in analogix_dp_bridge_mode_set()
/drivers/video/
Dhdmi.c513 else if (frame->vic != 0 || frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) in hdmi_vendor_infoframe_length()
527 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) in hdmi_vendor_infoframe_check_only()
600 } else if (frame->vic) { in hdmi_vendor_infoframe_pack_only()
602 ptr[8] = frame->vic; in hdmi_vendor_infoframe_pack_only()
1493 if (hvf->vic == 0 && hvf->s3d_struct == HDMI_3D_STRUCTURE_INVALID) { in hdmi_vendor_any_infoframe_log()
1498 if (hvf->vic) in hdmi_vendor_any_infoframe_log()
1499 hdmi_log(" HDMI VIC: %u\n", hvf->vic); in hdmi_vendor_any_infoframe_log()
1766 hvf->vic = ptr[4]; in hdmi_vendor_any_infoframe_unpack()
/drivers/gpu/drm/nouveau/nvkm/engine/vic/
DKbuild2 #nvkm-y += nvkm/engine/vic/base.o
/drivers/gpu/drm/omapdrm/dss/
Dhdmi5_core.c373 unsigned int vic; in hdmi_core_write_avi_infoframe() local
397 vic = ptr[3]; in hdmi_core_write_avi_infoframe()
412 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); in hdmi_core_write_avi_infoframe()
576 char vic = cfg->infoframe.video_code; in hdmi5_configure() local
579 range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED : in hdmi5_configure()
/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.c161 int vic; member
1916 if (hdmi->vic == 39) in hdmi_av_composer()
2137 hdmi->vic = drm_match_cea_mode(mode); in dw_hdmi_setup()
2139 if (!hdmi->vic) { in dw_hdmi_setup()
2142 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); in dw_hdmi_setup()
2145 if ((hdmi->vic == 6) || (hdmi->vic == 7) || in dw_hdmi_setup()
2146 (hdmi->vic == 21) || (hdmi->vic == 22) || in dw_hdmi_setup()
2147 (hdmi->vic == 2) || (hdmi->vic == 3) || in dw_hdmi_setup()
2148 (hdmi->vic == 17) || (hdmi->vic == 18)) in dw_hdmi_setup()
/drivers/gpu/drm/msm/dp/
Ddp_panel.h51 u32 vic; member
/drivers/gpu/drm/nouveau/nvkm/engine/
DKbuild24 include $(src)/nvkm/engine/vic/Kbuild
/drivers/gpu/drm/nouveau/include/nvkm/core/
Dlayout.h52 NVKM_LAYOUT_ONCE(NVKM_ENGINE_VIC , struct nvkm_engine , vic)
/drivers/gpu/drm/bridge/
Dlontium-lt9611.c59 u32 vic; member
360 regmap_write(lt9611->regmap, 0x8443, 0x46 - lt9611->vic); in lt9611_hdmi_tx_digital()
361 regmap_write(lt9611->regmap, 0x8447, lt9611->vic); in lt9611_hdmi_tx_digital()
930 lt9611->vic = avi_frame.video_code; in lt9611_bridge_mode_set()
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5_core.c417 unsigned vic; in hdmi_core_write_avi_infoframe() local
441 vic = ptr[3]; in hdmi_core_write_avi_infoframe()
456 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); in hdmi_core_write_avi_infoframe()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c2252 unsigned int vic = pipe_ctx->stream->timing.vic; in set_avi_info_frame() local
2425 vic = 95; in set_avi_info_frame()
2428 vic = 94; in set_avi_info_frame()
2431 vic = 93; in set_avi_info_frame()
2434 vic = 98; in set_avi_info_frame()
2441 hdmi_info.bits.VIC0_VIC7 = vic; in set_avi_info_frame()
2442 if (vic >= 128) in set_avi_info_frame()
/drivers/media/v4l2-core/
Dv4l2-dv-timings.c239 bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic) in v4l2_find_dv_timings_cea861_vic() argument
248 bt->cea861_vic == vic) { in v4l2_find_dv_timings_cea861_vic()
892 bool is_ce = avi->video_code || (hdmi && hdmi->vic); in v4l2_hdmi_rx_colorimetry()

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