| /drivers/clk/mediatek/ |
| D | clk-mt7986-apmixed.c | 27 _div_table, _parent_name) \ argument
34 .pcw_shift = _pcw_shift, .div_table = _div_table, \
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| D | clk-mt7629.c | 27 _pcw_shift, _div_table, _parent_name) { \ argument
42 .div_table = _div_table, \
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| D | clk-mt7622.c | 27 _pcw_shift, _div_table, _parent_name) { \ argument
42 .div_table = _div_table, \
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| D | clk-mt6797.c | 602 _pcw_shift, _div_table) { \ argument
617 .div_table = _div_table, \
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| D | clk-mt8516.c | 703 _pcw_shift, _div_table) { \ argument
718 .div_table = _div_table, \
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| D | clk-mt6765.c | 671 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\ argument
690 .div_table = _div_table, \
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| D | clk-mt8167.c | 985 _pcw_shift, _div_table) { \ argument
1000 .div_table = _div_table, \
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| D | clk-mt6779.c | 1150 _pcw_chg_reg, _div_table) { \ argument
1170 .div_table = _div_table, \
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| D | clk-mt8183.c | 1069 _pcw_chg_reg, _div_table) { \ argument
1089 .div_table = _div_table, \
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| D | clk-mt2712.c | 1134 _div_table) { \ argument
1151 .div_table = _div_table, \
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| D | clk-mt8365.c | 766 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ argument
787 .div_table = _div_table, \
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| D | clk-mt8173.c | 959 _pcw_shift, _div_table) { \ argument
974 .div_table = _div_table, \
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| /drivers/clk/ |
| D | clk-stm32mp1.c | 1194 _div_flags, _div_table)\ argument
1205 .table = _div_table,\
1320 _div_flags, _div_table, _ops)\ argument
1327 .table = _div_table,\
1332 #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\ argument
1334 _div_flags, _div_table, NULL)\
1336 #define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\ argument
1338 _div_flags, _div_table, &rtc_div_clk_ops)
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