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Searched refs:spi_parents (Results 1 – 20 of 20) sorted by relevance

/drivers/clk/mediatek/
Dclk-mt7986-topckgen.c78 static const char *const spi_parents[] __initconst = { variable
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
183 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
Dclk-mt2701.c222 static const char * const spi_parents[] = { variable
509 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
580 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
582 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
Dclk-mt6795-topckgen.c296 static const char * const spi_parents[] = { variable
467 TOP_MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x60, 16, 3, 23, 0),
Dclk-mt8186-topckgen.c122 static const char * const spi_parents[] = { variable
532 spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
Dclk-mt8135.c219 static const char * const spi_parents[] __initconst = { variable
375 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
Dclk-mt6797.c163 static const char * const spi_parents[] = { variable
341 MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
Dclk-mt8516.c314 static const char * const spi_parents[] __initconst = { variable
422 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
Dclk-mt8195-topckgen.c327 static const char * const spi_parents[] = { variable
925 spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
Dclk-mt6765.c226 static const char * const spi_parents[] = { variable
403 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
Dclk-mt8167.c474 static const char * const spi_parents[] __initconst = { variable
612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
Dclk-mt6779.c361 static const char * const spi_parents[] = { variable
688 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
Dclk-mt8183.c331 static const char * const spi_parents[] = { variable
572 spi_parents, 0x70,
Dclk-mt2712.c319 static const char * const spi_parents[] = { variable
760 spi_parents, 0x060, 16, 3, 23),
Dclk-mt8365.c157 static const char * const spi_parents[] = { variable
439 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
Dclk-mt8192.c273 static const char * const spi_parents[] = { variable
607 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
Dclk-mt8173.c231 static const char * const spi_parents[] __initconst = { variable
555 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
/drivers/clk/sunxi-ng/
Dccu-sun20i-d1.c472 static const struct clk_parent_data spi_parents[] = { variable
479 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
486 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
/drivers/clk/sprd/
Dsc9863a-clk.c934 static const struct clk_parent_data spi_parents[] = { variable
940 static SPRD_COMP_CLK_DATA(ap_spi0, "ap-spi0", spi_parents, 0x74,
942 static SPRD_COMP_CLK_DATA(ap_spi1, "ap-spi1", spi_parents, 0x78,
944 static SPRD_COMP_CLK_DATA(ap_spi2, "ap-spi2", spi_parents, 0x7c,
946 static SPRD_COMP_CLK_DATA(ap_spi3, "ap-spi3", spi_parents, 0x80,
Dsc9860-clk.c415 static const char * const spi_parents[] = { "ext-26m", "twpll-128m", variable
417 static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c,
419 static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60,
421 static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64,
423 static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68,
Dums512-clk.c508 static const struct clk_parent_data spi_parents[] = { variable
514 static SPRD_COMP_CLK_DATA(ap_spi0_clk, "ap-spi0-clk", spi_parents,
516 static SPRD_COMP_CLK_DATA(ap_spi1_clk, "ap-spi1-clk", spi_parents,
518 static SPRD_COMP_CLK_DATA(ap_spi2_clk, "ap-spi2-clk", spi_parents,
520 static SPRD_COMP_CLK_DATA(ap_spi3_clk, "ap-spi3-clk", spi_parents,