/drivers/clk/mediatek/ |
D | clk-mt7986-topckgen.c | 78 static const char *const spi_parents[] __initconst = { variable 181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 183 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
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D | clk-mt2701.c | 222 static const char * const spi_parents[] = { variable 509 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 580 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 582 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
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D | clk-mt6795-topckgen.c | 296 static const char * const spi_parents[] = { variable 467 TOP_MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x60, 16, 3, 23, 0),
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D | clk-mt8186-topckgen.c | 122 static const char * const spi_parents[] = { variable 532 spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
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D | clk-mt8135.c | 219 static const char * const spi_parents[] __initconst = { variable 375 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
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D | clk-mt6797.c | 163 static const char * const spi_parents[] = { variable 341 MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
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D | clk-mt8516.c | 314 static const char * const spi_parents[] __initconst = { variable 422 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
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D | clk-mt8195-topckgen.c | 327 static const char * const spi_parents[] = { variable 925 spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
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D | clk-mt6765.c | 226 static const char * const spi_parents[] = { variable 403 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
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D | clk-mt8167.c | 474 static const char * const spi_parents[] __initconst = { variable 612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
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D | clk-mt6779.c | 361 static const char * const spi_parents[] = { variable 688 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
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D | clk-mt8183.c | 331 static const char * const spi_parents[] = { variable 572 spi_parents, 0x70,
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D | clk-mt2712.c | 319 static const char * const spi_parents[] = { variable 760 spi_parents, 0x060, 16, 3, 23),
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D | clk-mt8365.c | 157 static const char * const spi_parents[] = { variable 439 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
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D | clk-mt8192.c | 273 static const char * const spi_parents[] = { variable 607 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
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D | clk-mt8173.c | 231 static const char * const spi_parents[] __initconst = { variable 555 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
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/drivers/clk/sunxi-ng/ |
D | ccu-sun20i-d1.c | 472 static const struct clk_parent_data spi_parents[] = { variable 479 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940, 486 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
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/drivers/clk/sprd/ |
D | sc9863a-clk.c | 934 static const struct clk_parent_data spi_parents[] = { variable 940 static SPRD_COMP_CLK_DATA(ap_spi0, "ap-spi0", spi_parents, 0x74, 942 static SPRD_COMP_CLK_DATA(ap_spi1, "ap-spi1", spi_parents, 0x78, 944 static SPRD_COMP_CLK_DATA(ap_spi2, "ap-spi2", spi_parents, 0x7c, 946 static SPRD_COMP_CLK_DATA(ap_spi3, "ap-spi3", spi_parents, 0x80,
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D | sc9860-clk.c | 415 static const char * const spi_parents[] = { "ext-26m", "twpll-128m", variable 417 static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c, 419 static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60, 421 static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64, 423 static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68,
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D | ums512-clk.c | 508 static const struct clk_parent_data spi_parents[] = { variable 514 static SPRD_COMP_CLK_DATA(ap_spi0_clk, "ap-spi0-clk", spi_parents, 516 static SPRD_COMP_CLK_DATA(ap_spi1_clk, "ap-spi1-clk", spi_parents, 518 static SPRD_COMP_CLK_DATA(ap_spi2_clk, "ap-spi2-clk", spi_parents, 520 static SPRD_COMP_CLK_DATA(ap_spi3_clk, "ap-spi3-clk", spi_parents,
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