| /drivers/iio/dac/ |
| D | ad5592r-base.c | 25 struct ad5592r_state *st = gpiochip_get_data(chip); in ad5592r_gpio_get() local
29 mutex_lock(&st->gpio_lock); in ad5592r_gpio_get()
31 if (st->gpio_out & BIT(offset)) in ad5592r_gpio_get()
32 val = st->gpio_val; in ad5592r_gpio_get()
34 ret = st->ops->gpio_read(st, &val); in ad5592r_gpio_get()
36 mutex_unlock(&st->gpio_lock); in ad5592r_gpio_get()
46 struct ad5592r_state *st = gpiochip_get_data(chip); in ad5592r_gpio_set() local
48 mutex_lock(&st->gpio_lock); in ad5592r_gpio_set()
51 st->gpio_val |= BIT(offset); in ad5592r_gpio_set()
53 st->gpio_val &= ~BIT(offset); in ad5592r_gpio_set()
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| D | ad5758.c | 186 static int ad5758_spi_reg_read(struct ad5758_state *st, unsigned int addr) in ad5758_spi_reg_read() argument
190 .tx_buf = &st->d32[0], in ad5758_spi_reg_read()
194 .tx_buf = &st->d32[1], in ad5758_spi_reg_read()
195 .rx_buf = &st->d32[2], in ad5758_spi_reg_read()
201 st->d32[0] = cpu_to_be32( in ad5758_spi_reg_read()
204 st->d32[1] = cpu_to_be32(AD5758_WR_FLAG_MSK(AD5758_NOP) << 24); in ad5758_spi_reg_read()
206 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); in ad5758_spi_reg_read()
210 return (be32_to_cpu(st->d32[2]) >> 8) & 0xFFFF; in ad5758_spi_reg_read()
213 static int ad5758_spi_reg_write(struct ad5758_state *st, in ad5758_spi_reg_write() argument
217 st->d32[0] = cpu_to_be32((AD5758_WR_FLAG_MSK(addr) << 24) | in ad5758_spi_reg_write()
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| /drivers/macintosh/ |
| D | windfarm_pid.c | 25 void wf_pid_init(struct wf_pid_state *st, struct wf_pid_param *param) in wf_pid_init() argument
27 memset(st, 0, sizeof(struct wf_pid_state)); in wf_pid_init()
28 st->param = *param; in wf_pid_init()
29 st->first = 1; in wf_pid_init()
33 s32 wf_pid_run(struct wf_pid_state *st, s32 new_sample) in wf_pid_run() argument
37 int i, hlen = st->param.history_len; in wf_pid_run()
40 error = new_sample - st->param.itarget; in wf_pid_run()
43 if (st->first) { in wf_pid_run()
45 st->samples[i] = new_sample; in wf_pid_run()
46 st->errors[i] = error; in wf_pid_run()
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| /drivers/iio/adc/ |
| D | ad7606.c | 52 static int ad7606_reset(struct ad7606_state *st) in ad7606_reset() argument
54 if (st->gpio_reset) { in ad7606_reset()
55 gpiod_set_value(st->gpio_reset, 1); in ad7606_reset()
57 gpiod_set_value(st->gpio_reset, 0); in ad7606_reset()
69 struct ad7606_state *st = iio_priv(indio_dev); in ad7606_reg_access() local
72 mutex_lock(&st->lock); in ad7606_reg_access()
74 ret = st->bops->reg_read(st, reg); in ad7606_reg_access()
80 ret = st->bops->reg_write(st, reg, writeval); in ad7606_reg_access()
83 mutex_unlock(&st->lock); in ad7606_reg_access()
87 static int ad7606_read_samples(struct ad7606_state *st) in ad7606_read_samples() argument
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| D | at91_adc.c | 136 #define AT91_ADC_CHAN(st, ch) \ argument
137 (st->registers->channel_base + (ch * 4))
138 #define at91_adc_readl(st, reg) \ argument
139 (readl_relaxed(st->reg_base + reg))
140 #define at91_adc_writel(st, reg, val) \ argument
141 (writel_relaxed(val, st->reg_base + reg))
268 struct at91_adc_state *st = iio_priv(idev); in at91_adc_trigger_handler() local
276 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); in at91_adc_trigger_handler()
280 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); in at91_adc_trigger_handler()
285 at91_adc_readl(st, AT91_ADC_LCDR); in at91_adc_trigger_handler()
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| D | at91-sama5d2_adc.c | 428 #define at91_adc_readl(st, reg) \ argument
429 readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg)
430 #define at91_adc_read_chan(st, reg) \ argument
431 readl_relaxed((st)->base + reg)
432 #define at91_adc_writel(st, reg, val) \ argument
433 writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
777 struct at91_adc_state *st = iio_priv(indio_dev); in at91_adc_active_scan_mask_to_reg() local
786 return mask & GENMASK(st->soc_info.platform->nr_channels, 0); in at91_adc_active_scan_mask_to_reg()
789 static void at91_adc_cor(struct at91_adc_state *st, in at91_adc_cor() argument
796 cur_cor = at91_adc_readl(st, COR); in at91_adc_cor()
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| D | ti-ads7950.c | 60 #define TI_ADS7950_MAN_CMD_SETTINGS(st) \ argument
61 (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
63 #define TI_ADS7950_GPIO_CMD_SETTINGS(st) \ argument
64 (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
286 struct ti_ads7950_state *st = iio_priv(indio_dev); in ti_ads7950_update_scan_mode() local
292 st->tx_buf[len++] = cmd; in ti_ads7950_update_scan_mode()
296 st->tx_buf[len++] = 0; in ti_ads7950_update_scan_mode()
297 st->tx_buf[len++] = 0; in ti_ads7950_update_scan_mode()
299 st->ring_xfer.len = len * 2; in ti_ads7950_update_scan_mode()
308 struct ti_ads7950_state *st = iio_priv(indio_dev); in ti_ads7950_trigger_handler() local
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| D | ad7887.c | 83 struct ad7887_state *st = iio_priv(indio_dev); in ad7887_ring_preenable() local
88 st->ring_msg = &st->msg[AD7887_CH0]; in ad7887_ring_preenable()
91 st->ring_msg = &st->msg[AD7887_CH1]; in ad7887_ring_preenable()
93 spi_sync(st->spi, st->ring_msg); in ad7887_ring_preenable()
96 st->ring_msg = &st->msg[AD7887_CH0_CH1]; in ad7887_ring_preenable()
105 struct ad7887_state *st = iio_priv(indio_dev); in ad7887_ring_postdisable() local
108 return spi_sync(st->spi, &st->msg[AD7887_CH0]); in ad7887_ring_postdisable()
115 struct ad7887_state *st = iio_priv(indio_dev); in ad7887_trigger_handler() local
118 b_sent = spi_sync(st->spi, st->ring_msg); in ad7887_trigger_handler()
122 iio_push_to_buffers_with_timestamp(indio_dev, st->data, in ad7887_trigger_handler()
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| D | ad7298.c | 106 struct ad7298_state *st = iio_priv(indio_dev); in ad7298_update_scan_mode() local
114 command = AD7298_WRITE | st->ext_ref; in ad7298_update_scan_mode()
120 st->tx_buf[0] = cpu_to_be16(command); in ad7298_update_scan_mode()
123 st->ring_xfer[0].tx_buf = &st->tx_buf[0]; in ad7298_update_scan_mode()
124 st->ring_xfer[0].len = 2; in ad7298_update_scan_mode()
125 st->ring_xfer[0].cs_change = 1; in ad7298_update_scan_mode()
126 st->ring_xfer[1].tx_buf = &st->tx_buf[1]; in ad7298_update_scan_mode()
127 st->ring_xfer[1].len = 2; in ad7298_update_scan_mode()
128 st->ring_xfer[1].cs_change = 1; in ad7298_update_scan_mode()
130 spi_message_init(&st->ring_msg); in ad7298_update_scan_mode()
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| D | ti-ads131e08.c | 162 static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd) in ads131e08_exec_cmd() argument
166 ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0); in ads131e08_exec_cmd()
168 dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd); in ads131e08_exec_cmd()
173 static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg) in ads131e08_read_reg() argument
178 .tx_buf = &st->tx_buf, in ads131e08_read_reg()
181 .value = st->sdecode_delay_us, in ads131e08_read_reg()
185 .rx_buf = &st->rx_buf, in ads131e08_read_reg()
190 st->tx_buf[0] = ADS131E08_CMD_RREG(reg); in ads131e08_read_reg()
191 st->tx_buf[1] = 0; in ads131e08_read_reg()
193 ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer)); in ads131e08_read_reg()
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| D | nau7802.c | 85 struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev)); in nau7802_show_scales() local
88 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in nau7802_show_scales()
90 st->scale_avail[i]); in nau7802_show_scales()
112 static int nau7802_set_gain(struct nau7802_state *st, int gain) in nau7802_set_gain() argument
116 mutex_lock(&st->lock); in nau7802_set_gain()
117 st->conversion_count = 0; in nau7802_set_gain()
119 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1); in nau7802_set_gain()
122 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1, in nau7802_set_gain()
127 mutex_unlock(&st->lock); in nau7802_set_gain()
132 static int nau7802_read_conversion(struct nau7802_state *st) in nau7802_read_conversion() argument
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| D | ad7192.c | 205 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set_syscalib_mode() local
207 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
215 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_get_syscalib_mode() local
217 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
225 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_syscalib() local
233 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
236 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
239 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
273 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_channel() local
275 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
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| /drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_private_obj.c | 11 komeda_component_state_reset(struct komeda_component_state *st) in komeda_component_state_reset() argument
13 st->binding_user = NULL; in komeda_component_state_reset()
14 st->affected_inputs = st->active_inputs; in komeda_component_state_reset()
15 st->active_inputs = 0; in komeda_component_state_reset()
16 st->changed_active_inputs = 0; in komeda_component_state_reset()
22 struct komeda_layer_state *st; in komeda_layer_atomic_duplicate_state() local
24 st = kmemdup(obj->state, sizeof(*st), GFP_KERNEL); in komeda_layer_atomic_duplicate_state()
25 if (!st) in komeda_layer_atomic_duplicate_state()
28 komeda_component_state_reset(&st->base); in komeda_layer_atomic_duplicate_state()
29 __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); in komeda_layer_atomic_duplicate_state()
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| /drivers/staging/iio/frequency/ |
| D | ad9832.c | 129 static int ad9832_write_frequency(struct ad9832_state *st, in ad9832_write_frequency() argument
134 if (fout > (clk_get_rate(st->mclk) / 2)) in ad9832_write_frequency()
137 regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout); in ad9832_write_frequency()
139 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) | in ad9832_write_frequency()
142 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) | in ad9832_write_frequency()
145 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) | in ad9832_write_frequency()
148 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) | in ad9832_write_frequency()
152 return spi_sync(st->spi, &st->freq_msg); in ad9832_write_frequency()
155 static int ad9832_write_phase(struct ad9832_state *st, in ad9832_write_phase() argument
161 st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) | in ad9832_write_phase()
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| D | ad9834.c | 109 static int ad9834_write_frequency(struct ad9834_state *st, in ad9834_write_frequency() argument
115 clk_freq = clk_get_rate(st->mclk); in ad9834_write_frequency()
122 st->freq_data[0] = cpu_to_be16(addr | (regval & in ad9834_write_frequency()
124 st->freq_data[1] = cpu_to_be16(addr | ((regval >> in ad9834_write_frequency()
128 return spi_sync(st->spi, &st->freq_msg); in ad9834_write_frequency()
131 static int ad9834_write_phase(struct ad9834_state *st, in ad9834_write_phase() argument
136 st->data = cpu_to_be16(addr | phase); in ad9834_write_phase()
138 return spi_sync(st->spi, &st->msg); in ad9834_write_phase()
147 struct ad9834_state *st = iio_priv(indio_dev); in ad9834_write() local
156 mutex_lock(&st->lock); in ad9834_write()
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| /drivers/iio/accel/ |
| D | sca3000.c | 277 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) in sca3000_write_reg() argument
279 st->tx[0] = SCA3000_WRITE_REG(address); in sca3000_write_reg()
280 st->tx[1] = val; in sca3000_write_reg()
281 return spi_write(st->us, st->tx, 2); in sca3000_write_reg()
284 static int sca3000_read_data_short(struct sca3000_state *st, in sca3000_read_data_short() argument
291 .tx_buf = st->tx, in sca3000_read_data_short()
294 .rx_buf = st->rx, in sca3000_read_data_short()
297 st->tx[0] = SCA3000_READ_REG(reg_address_high); in sca3000_read_data_short()
299 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer)); in sca3000_read_data_short()
308 static int sca3000_reg_lock_on(struct sca3000_state *st) in sca3000_reg_lock_on() argument
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| D | adxl367.c | 273 static int adxl367_set_measure_en(struct adxl367_state *st, bool en) in adxl367_set_measure_en() argument
279 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL, in adxl367_set_measure_en()
296 static void adxl367_scale_act_thresholds(struct adxl367_state *st, in adxl367_scale_act_thresholds() argument
300 st->act_threshold = st->act_threshold in adxl367_scale_act_thresholds()
303 st->inact_threshold = st->inact_threshold in adxl367_scale_act_thresholds()
308 static int _adxl367_set_act_threshold(struct adxl367_state *st, in _adxl367_set_act_threshold() argument
318 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK, in _adxl367_set_act_threshold()
321 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK, in _adxl367_set_act_threshold()
325 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf, in _adxl367_set_act_threshold()
326 sizeof(st->act_threshold_buf)); in _adxl367_set_act_threshold()
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| /drivers/iio/imu/inv_icm42600/ |
| D | inv_icm42600_core.c | 96 const struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); in inv_icm42600_get_mount_matrix() local
98 return &st->orientation; in inv_icm42600_get_mount_matrix()
137 static int inv_icm42600_set_pwr_mgmt0(struct inv_icm42600_state *st, in inv_icm42600_set_pwr_mgmt0() argument
142 enum inv_icm42600_sensor_mode oldgyro = st->conf.gyro.mode; in inv_icm42600_set_pwr_mgmt0()
143 enum inv_icm42600_sensor_mode oldaccel = st->conf.accel.mode; in inv_icm42600_set_pwr_mgmt0()
144 bool oldtemp = st->conf.temp_en; in inv_icm42600_set_pwr_mgmt0()
157 ret = regmap_write(st->map, INV_ICM42600_REG_PWR_MGMT0, val); in inv_icm42600_set_pwr_mgmt0()
161 st->conf.gyro.mode = gyro; in inv_icm42600_set_pwr_mgmt0()
162 st->conf.accel.mode = accel; in inv_icm42600_set_pwr_mgmt0()
163 st->conf.temp_en = temp; in inv_icm42600_set_pwr_mgmt0()
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| D | inv_icm42600_buffer.c | 100 void inv_icm42600_buffer_update_fifo_period(struct inv_icm42600_state *st) in inv_icm42600_buffer_update_fifo_period() argument
104 if (st->fifo.en & INV_ICM42600_SENSOR_GYRO) in inv_icm42600_buffer_update_fifo_period()
105 period_gyro = inv_icm42600_odr_to_period(st->conf.gyro.odr); in inv_icm42600_buffer_update_fifo_period()
109 if (st->fifo.en & INV_ICM42600_SENSOR_ACCEL) in inv_icm42600_buffer_update_fifo_period()
110 period_accel = inv_icm42600_odr_to_period(st->conf.accel.odr); in inv_icm42600_buffer_update_fifo_period()
119 st->fifo.period = period; in inv_icm42600_buffer_update_fifo_period()
122 int inv_icm42600_buffer_set_fifo_en(struct inv_icm42600_state *st, in inv_icm42600_buffer_set_fifo_en() argument
142 ret = regmap_update_bits(st->map, INV_ICM42600_REG_FIFO_CONFIG1, mask, val); in inv_icm42600_buffer_set_fifo_en()
146 st->fifo.en = fifo_en; in inv_icm42600_buffer_set_fifo_en()
147 inv_icm42600_buffer_update_fifo_period(st); in inv_icm42600_buffer_set_fifo_en()
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| /drivers/iio/addac/ |
| D | ad74413r.c | 170 struct ad74413r_state *st = context; in ad74413r_reg_write() local
172 ad74413r_format_reg_write(reg, val, st->reg_tx_buf); in ad74413r_reg_write()
174 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE); in ad74413r_reg_write()
177 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf) in ad74413r_crc_check() argument
182 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n", in ad74413r_crc_check()
192 struct ad74413r_state *st = context; in ad74413r_reg_read() local
195 .tx_buf = st->reg_tx_buf, in ad74413r_reg_read()
200 .rx_buf = st->reg_rx_buf, in ad74413r_reg_read()
207 st->reg_tx_buf); in ad74413r_reg_read()
209 ret = spi_sync_transfer(st->spi, reg_read_xfer, in ad74413r_reg_read()
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| /drivers/staging/iio/resolver/ |
| D | ad2s1210.c | 108 struct ad2s1210_state *st) in ad2s1210_set_mode() argument
110 gpiod_set_value(st->gpios[AD2S1210_A0], ad2s1210_mode_vals[mode][0]); in ad2s1210_set_mode()
111 gpiod_set_value(st->gpios[AD2S1210_A1], ad2s1210_mode_vals[mode][1]); in ad2s1210_set_mode()
112 st->mode = mode; in ad2s1210_set_mode()
116 static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data) in ad2s1210_config_write() argument
120 ad2s1210_set_mode(MOD_CONFIG, st); in ad2s1210_config_write()
121 st->tx[0] = data; in ad2s1210_config_write()
122 ret = spi_write(st->sdev, st->tx, 1); in ad2s1210_config_write()
130 static int ad2s1210_config_read(struct ad2s1210_state *st, in ad2s1210_config_read() argument
136 .rx_buf = &st->rx[0], in ad2s1210_config_read()
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| /drivers/iio/frequency/ |
| D | adf4350.c | 73 static int adf4350_sync_config(struct adf4350_state *st) in adf4350_sync_config() argument
78 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
87 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
88 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
91 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
92 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
93 i, (u32)st->regs[i] | i); in adf4350_sync_config()
103 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_reg_access() local
109 mutex_lock(&st->lock); in adf4350_reg_access()
111 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); in adf4350_reg_access()
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| /drivers/iio/imu/inv_mpu6050/ |
| D | inv_mpu_core.c | 276 static int inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state *st, bool sleep, in inv_mpu6050_pwr_mgmt_1_write() argument
282 clock = st->chip_config.clk; in inv_mpu6050_pwr_mgmt_1_write()
284 temp_dis = !st->chip_config.temp_en; in inv_mpu6050_pwr_mgmt_1_write()
292 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val); in inv_mpu6050_pwr_mgmt_1_write()
293 return regmap_write(st->map, st->reg->pwr_mgmt_1, val); in inv_mpu6050_pwr_mgmt_1_write()
296 static int inv_mpu6050_clock_switch(struct inv_mpu6050_state *st, in inv_mpu6050_clock_switch() argument
301 switch (st->chip_type) { in inv_mpu6050_clock_switch()
306 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, clock, -1); in inv_mpu6050_clock_switch()
309 st->chip_config.clk = clock; in inv_mpu6050_clock_switch()
319 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, in inv_mpu6050_switch_engine() argument
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| D | inv_mpu_trigger.c | 11 struct inv_mpu6050_state *st = iio_priv(indio_dev); in inv_scan_query_mpu6050() local
20 st->chip_config.temp_fifo_enable = true; in inv_scan_query_mpu6050()
24 st->chip_config.gyro_fifo_enable = in inv_scan_query_mpu6050()
32 st->chip_config.accl_fifo_enable = in inv_scan_query_mpu6050()
40 st->chip_config.temp_fifo_enable = in inv_scan_query_mpu6050()
44 if (st->chip_config.gyro_fifo_enable) in inv_scan_query_mpu6050()
46 if (st->chip_config.accl_fifo_enable) in inv_scan_query_mpu6050()
48 if (st->chip_config.temp_fifo_enable) in inv_scan_query_mpu6050()
56 struct inv_mpu6050_state *st = iio_priv(indio_dev); in inv_scan_query_mpu9x50() local
62 if (st->magn_disabled) in inv_scan_query_mpu9x50()
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| /drivers/isdn/mISDN/ |
| D | stack.c | 21 _queue_message(struct mISDNstack *st, struct sk_buff *skb) in _queue_message() argument
28 skb_queue_tail(&st->msgq, skb); in _queue_message()
29 if (likely(!test_bit(mISDN_STACK_STOPPED, &st->status))) { in _queue_message()
30 test_and_set_bit(mISDN_STACK_WORK, &st->status); in _queue_message()
31 wake_up_interruptible(&st->workq); in _queue_message()
38 _queue_message(ch->st, skb); in mISDN_queue_message()
43 get_channel4id(struct mISDNstack *st, u_int id) in get_channel4id() argument
47 mutex_lock(&st->lmutex); in get_channel4id()
48 list_for_each_entry(ch, &st->layer2, list) { in get_channel4id()
54 mutex_unlock(&st->lmutex); in get_channel4id()
[all …]
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