| /drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4) argument
36 #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24) argument
37 #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) argument
38 #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) argument
41 #define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24) argument
42 #define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) argument
43 #define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8) argument
44 #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) argument
47 #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) argument
52 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) argument
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| /drivers/media/pci/solo6x10/ |
| D | solo6x10-regs.h | 34 #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) argument
36 #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) argument
41 #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) argument
49 #define SOLO_VCLK_SELECT(n) ((n)<<20) argument
50 #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) argument
51 #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12) argument
52 #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10) argument
53 #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8) argument
54 #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6) argument
55 #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4) argument
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| D | solo6x10-tw28.h | 19 #define TW_CHIP_OFFSET_ADDR(n) (TW_BASE_ADDR + (n)) argument
23 #define TW_HUE_ADDR(n) (0x07 | ((n) << 4)) argument
24 #define TW_SATURATION_ADDR(n) (0x08 | ((n) << 4)) argument
25 #define TW_CONTRAST_ADDR(n) (0x09 | ((n) << 4)) argument
26 #define TW_BRIGHTNESS_ADDR(n) (0x0a | ((n) << 4)) argument
28 #define TW_AUDIO_INPUT_GAIN_ADDR(n) (0x60 + ((n > 1) ? 1 : 0)) argument
32 #define TW286x_HUE_ADDR(n) (0x06 | ((n) << 4)) argument
33 #define TW286x_SATURATIONU_ADDR(n) (0x04 | ((n) << 4)) argument
34 #define TW286x_SATURATIONV_ADDR(n) (0x05 | ((n) << 4)) argument
35 #define TW286x_CONTRAST_ADDR(n) (0x02 | ((n) << 4)) argument
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| /drivers/gpu/drm/panel/ |
| D | panel-sitronix-st7789v.c | 23 #define ST7789V_RAMCTRL_EPF(n) (((n) & 3) << 4) argument
27 #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5) argument
32 #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f) argument
33 #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f) argument
36 #define ST7789V_PORCTRL_IDLE_BP(n) (((n) & 0xf) << 4) argument
37 #define ST7789V_PORCTRL_IDLE_FP(n) ((n) & 0xf) argument
38 #define ST7789V_PORCTRL_PARTIAL_BP(n) (((n) & 0xf) << 4) argument
39 #define ST7789V_PORCTRL_PARTIAL_FP(n) ((n) & 0xf) argument
42 #define ST7789V_GCTRL_VGHS(n) (((n) & 7) << 4) argument
43 #define ST7789V_GCTRL_VGLS(n) ((n) & 7) argument
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| /drivers/media/platform/nxp/imx8-isi/ |
| D | imx8-isi-regs.h | 17 #define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25) argument
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16) argument
24 #define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6) argument
26 #define CHNL_CTRL_SRC_TYPE(n) ((n) << 4) argument
30 #define CHNL_CTRL_SRC_INPUT(n) ((n) << 0) argument
35 #define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24) argument
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16) argument
89 #define CHNL_IMG_CTRL_DEINT(n) ((n) << 12) argument
97 #define CHNL_IMG_CTRL_DEC_X(n) ((n) << 10) argument
99 #define CHNL_IMG_CTRL_DEC_Y(n) ((n) << 8) argument
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| /drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 21 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000) argument
23 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3) argument
24 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7) argument
29 #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000) argument
34 #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000) argument
36 #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000) argument
40 #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000) argument
41 #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0) argument
42 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5) argument
43 #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000) argument
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.h | 37 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
39 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
41 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
43 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
45 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
47 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \ argument
49 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \ argument
51 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \ argument
53 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \ argument
55 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \ argument
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.h | 34 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
36 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
38 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
40 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
42 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
44 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \ argument
46 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \ argument
48 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \ argument
50 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \ argument
52 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \ argument
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| /drivers/media/platform/qcom/camss/ |
| D | camss-vfe-480.c | 27 static inline int reg_update_rdi(struct vfe_device *vfe, int n) in reg_update_rdi()
36 #define VFE_IRQ_MASK(n) ((IS_LITE ? 0x28 : 0x3c) + (n) * 4) argument
39 #define VFE_IRQ_CLEAR(n) ((IS_LITE ? 0x34 : 0x48) + (n) * 4) argument
40 #define VFE_IRQ_STATUS(n) ((IS_LITE ? 0x40 : 0x54) + (n) * 4) argument
49 #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) argument
50 static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n) in bus_irq_mask_0_rdi_rup()
56 static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) in bus_irq_mask_0_comp_done()
62 #define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) argument
63 #define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) argument
66 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) argument
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| D | camss-vfe-170.c | 50 #define MASK_0_RDI_REG_UPDATE(n) BIT((n) + 5) argument
51 #define MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) argument
52 #define MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) argument
59 #define MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) argument
60 #define MASK_1_RDI_SOF(n) BIT((n) + 29) argument
67 #define STATUS_0_RDI_REG_UPDATE(n) BIT((n) + 5) argument
68 #define STATUS_0_IMAGE_MASTER_PING_PONG(n) BIT((n) + 8) argument
69 #define STATUS_0_IMAGE_COMPOSITE_DONE(n) BIT((n) + 25) argument
75 #define STATUS_1_RDI_SOF(n) BIT((n) + 27) argument
98 #define REG_UPDATE_RDI(n) BIT(1 + (n)) argument
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| D | camss-csiphy-3ph-1-0.c | 18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) argument
20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) argument
22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) argument
23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) argument
26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n)) argument
29 #define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n)) argument
31 #define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n)) argument
33 #define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n)) argument
35 #define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n)) argument
37 #define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n)) argument
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| /drivers/gpu/drm/exynos/ |
| D | regs-decon5433.h | 12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4)) argument
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4)) argument
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20)) argument
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20)) argument
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20)) argument
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20)) argument
19 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20)) argument
20 #define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10)) argument
21 #define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10)) argument
22 #define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10)) argument
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| /drivers/gpu/drm/rockchip/ |
| D | inno_hdmi.h | 48 #define v_VIDEO_INPUT_FORMAT(n) (n << 1) argument
61 #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6) argument
62 #define v_VIDEO_INPUT_BITS(n) (n << 4) argument
63 #define v_VIDEO_INPUT_CSP(n) (n << 0) argument
73 #define v_VIDEO_AUTO_CSC(n) (n << 7) argument
75 #define v_VIDEO_C0_C2_SWAP(n) (n << 0) argument
88 #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4) argument
101 #define v_AVMUTE_CLEAR(n) (n << 7) argument
102 #define v_AVMUTE_ENABLE(n) (n << 6) argument
103 #define v_AUDIO_MUTE(n) (n << 1) argument
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| /drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 147 #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2) argument
148 #define XCVR_PSM_CAL_TMR(n) ((0x4002 | ((n) << 9)) << 2) argument
149 #define XCVR_PSM_A0IN_TMR(n) ((0x4003 | ((n) << 9)) << 2) argument
150 #define TX_TXCC_CAL_SCLR_MULT(n) ((0x4047 | ((n) << 9)) << 2) argument
151 #define TX_TXCC_CPOST_MULT_00(n) ((0x404c | ((n) << 9)) << 2) argument
152 #define TX_TXCC_CPOST_MULT_01(n) ((0x404d | ((n) << 9)) << 2) argument
153 #define TX_TXCC_CPOST_MULT_10(n) ((0x404e | ((n) << 9)) << 2) argument
154 #define TX_TXCC_CPOST_MULT_11(n) ((0x404f | ((n) << 9)) << 2) argument
155 #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2) argument
156 #define TX_TXCC_MGNFS_MULT_001(n) ((0x4051 | ((n) << 9)) << 2) argument
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| /drivers/staging/wlan-ng/ |
| D | p80211mgmt.h | 179 #define WLAN_GET_MGMT_CAP_INFO_ESS(n) ((n) & BIT(0)) argument
180 #define WLAN_GET_MGMT_CAP_INFO_IBSS(n) (((n) & BIT(1)) >> 1) argument
181 #define WLAN_GET_MGMT_CAP_INFO_CFPOLLABLE(n) (((n) & BIT(2)) >> 2) argument
182 #define WLAN_GET_MGMT_CAP_INFO_CFPOLLREQ(n) (((n) & BIT(3)) >> 3) argument
183 #define WLAN_GET_MGMT_CAP_INFO_PRIVACY(n) (((n) & BIT(4)) >> 4) argument
185 #define WLAN_GET_MGMT_CAP_INFO_SHORT(n) (((n) & BIT(5)) >> 5) argument
186 #define WLAN_GET_MGMT_CAP_INFO_PBCC(n) (((n) & BIT(6)) >> 6) argument
187 #define WLAN_GET_MGMT_CAP_INFO_AGILITY(n) (((n) & BIT(7)) >> 7) argument
189 #define WLAN_SET_MGMT_CAP_INFO_ESS(n) (n) argument
190 #define WLAN_SET_MGMT_CAP_INFO_IBSS(n) ((n) << 1) argument
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| /drivers/mailbox/ |
| D | sun6i-msgbox.c | 22 #define CTRL_REG(n) (0x0000 + 0x4 * ((n) / 4)) argument
23 #define CTRL_RX(n) BIT(0 + 8 * ((n) % 4)) argument
24 #define CTRL_TX(n) BIT(4 + 8 * ((n) % 4)) argument
31 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
33 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
36 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
39 #define MSG_STAT_REG(n) (0x0140 + 0x4 * (n)) argument
42 #define MSG_DATA_REG(n) (0x0180 + 0x4 * (n)) argument
70 int n; in sun6i_msgbox_irq() local
102 int n = channel_number(chan); in sun6i_msgbox_send_data() local
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| /drivers/usb/gadget/udc/ |
| D | fusb300_udc.h | 21 #define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30) argument
22 #define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30) argument
23 #define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30) argument
24 #define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30) argument
25 #define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30) argument
54 #define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10) argument
55 #define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10) argument
56 #define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10) argument
57 #define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10) argument
60 #define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10) argument
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| /drivers/gpu/drm/sun4i/ |
| D | sun6i_mipi_dsi.c | 39 #define SUN6I_DSI_BASIC_CTL_TRAIL_INV(n) (((n) & 0xf) << 4) argument
52 #define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4) argument
58 #define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16) argument
59 #define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff) argument
62 #define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16) argument
63 #define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff) argument
65 #define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04) argument
66 #define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28) argument
67 #define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24) argument
68 #define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20) argument
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| /drivers/gpu/drm/mxsfb/ |
| D | lcdif_regs.h | 150 #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16) argument
152 #define DISP_SIZE_DELTA_X(n) ((n) & 0xffff) argument
155 #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16) argument
157 #define HSYN_PARA_FP_H(n) ((n) & 0xffff) argument
160 #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16) argument
162 #define VSYN_PARA_FP_V(n) ((n) & 0xffff) argument
165 #define VSYN_HSYN_WIDTH_PW_V(n) (((n) & 0xffff) << 16) argument
167 #define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff) argument
188 #define CTRLDESCL0_1_HEIGHT(n) (((n) & 0xffff) << 16) argument
190 #define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff) argument
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| /drivers/vhost/ |
| D | test.c | 43 static void handle_vq(struct vhost_test *n) in handle_vq()
100 struct vhost_test *n = container_of(vq->dev, struct vhost_test, dev); in handle_vq_kick() local
107 struct vhost_test *n = kmalloc(sizeof *n, GFP_KERNEL); in vhost_test_open() local
130 static void *vhost_test_stop_vq(struct vhost_test *n, in vhost_test_stop_vq()
142 static void vhost_test_stop(struct vhost_test *n, void **privatep) in vhost_test_stop()
147 static void vhost_test_flush(struct vhost_test *n) in vhost_test_flush()
154 struct vhost_test *n = f->private_data; in vhost_test_release() local
166 static long vhost_test_run(struct vhost_test *n, int test) in vhost_test_run()
217 static long vhost_test_reset_owner(struct vhost_test *n) in vhost_test_reset_owner()
241 static int vhost_test_set_features(struct vhost_test *n, u64 features) in vhost_test_set_features()
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| /drivers/crypto/inside-secure/ |
| D | safexcel.h | 40 #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3) argument
41 #define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3) argument
147 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n))) argument
148 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n))) argument
149 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n))) argument
150 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n))) argument
151 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n))) argument
152 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n))) argument
153 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n))) argument
167 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) argument
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| /drivers/usb/dwc3/ |
| D | core.h | 133 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) argument
134 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) argument
136 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) argument
138 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) argument
140 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) argument
141 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) argument
143 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) argument
144 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) argument
145 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) argument
146 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) argument
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| D | gadget.h | 23 #define DWC3_DEPCFG_INT_NUM(n) (((n) & 0x1f) << 0) argument
29 #define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16) argument
31 #define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25) argument
36 #define DWC3_DEPCFG_EP_TYPE(n) (((n) & 0x3) << 1) argument
37 #define DWC3_DEPCFG_MAX_PACKET_SIZE(n) (((n) & 0x7ff) << 3) argument
38 #define DWC3_DEPCFG_FIFO_NUMBER(n) (((n) & 0x1f) << 17) argument
39 #define DWC3_DEPCFG_BURST_SIZE(n) (((n) & 0xf) << 22) argument
40 #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) argument
49 #define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) argument
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| /drivers/gpu/drm/bridge/ |
| D | chipone-icn6211.c | 30 #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */ argument
31 #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */ argument
32 #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */ argument
38 #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */ argument
39 #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */ argument
49 #define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4) argument
50 #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6) argument
51 #define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8) argument
56 #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4) argument
74 #define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */ argument
[all …]
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| /drivers/media/cec/core/ |
| D | cec-notifier.c | 54 struct cec_notifier *n; in cec_notifier_get_conn() local
90 struct cec_notifier *n = in cec_notifier_release() local
98 static void cec_notifier_put(struct cec_notifier *n) in cec_notifier_put()
109 struct cec_notifier *n = cec_notifier_get_conn(hdmi_dev, port_name); in cec_notifier_conn_register() local
130 void cec_notifier_conn_unregister(struct cec_notifier *n) in cec_notifier_conn_unregister()
152 struct cec_notifier *n; in cec_notifier_cec_adap_register() local
172 void cec_notifier_cec_adap_unregister(struct cec_notifier *n, in cec_notifier_cec_adap_unregister()
186 void cec_notifier_set_phys_addr(struct cec_notifier *n, u16 pa) in cec_notifier_set_phys_addr()
199 void cec_notifier_set_phys_addr_from_edid(struct cec_notifier *n, in cec_notifier_set_phys_addr_from_edid()
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