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/kernel/linux/linux-5.10/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
21 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
51 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
64 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
107 /* Relative to priv->regmap */
109 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
128 * A lane is described by the following bitfields:
[all …]
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
41 #define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
42 #define COMPHY_FW_SPEED_2_5G 1
58 unsigned int lane; member
67 .lane = _lane, \
81 /* lane 0 */
84 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
86 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
[all …]
Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
63 if (priv->conf) { in a38x_set_conf()
64 conf = readl_relaxed(priv->conf); in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
69 writel(conf, priv->conf); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
[all …]
/kernel/linux/linux-4.19/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 /* Relative to priv->base */
18 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
47 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
60 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
103 /* Relative to priv->regmap */
105 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
119 unsigned lane; member
126 .lane = _lane, \
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/b53/
Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
39 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
42 WARN_ON(lane > 1); in b53_serdes_set_lane()
45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
46 dev->serdes_lane = lane; in b53_serdes_set_lane()
49 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
52 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
59 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c16 link->ctx->logger
32 /* to avoid infinite loop where-in the receiver
53 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in wait_for_training_aux_rd_interval()
54 /* DP 1.2 or later - retrieve delay through in wait_for_training_aux_rd_interval()
82 1); in dpcd_set_training_pattern()
95 (lt_settings->link_settings.link_rate); in dpcd_set_link_settings()
102 (lt_settings->link_settings.link_spread); in dpcd_set_link_settings()
105 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
107 lane_count_set.bits.ENHANCED_FRAMING = 1; in dpcd_set_link_settings()
110 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED; in dpcd_set_link_settings()
[all …]
/kernel/linux/linux-5.10/drivers/phy/tegra/
Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
46 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
47 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
48 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
55 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
[all …]
Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
49 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
56 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
57 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
58 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
59 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
61 (1 << (1 + (x) * 3))
62 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
65 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
[all …]
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
35 #define PORT_XUSB 1
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
94 #define HSIC_PD_TX_DATA0 BIT(1)
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
[all …]
/kernel/linux/linux-4.19/drivers/phy/tegra/
Dxusb-tegra124.c47 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
54 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
55 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
56 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
57 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
59 (1 << (17 + (x) * 4))
60 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
63 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
65 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
68 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
[all …]
Dxusb-tegra210.c33 ((x) ? (11 + ((x) - 1) * 6) : 0)
54 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
60 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
61 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
62 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
63 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
65 (1 << (1 + (x) * 3))
66 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
69 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
70 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/kernel/linux/linux-4.19/drivers/phy/
Dphy-xgene.c2 * AppliedMicro X-Gene Multi-purpose PHY driver
22 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
31 * -----------------
32 * | Internal | |------|
33 * | Ref PLL CMU |----| | ------------- ---------
34 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
35 * | | | | ---------
36 * External Clock ------| | -------------
37 * |------|
84 #define SSC_ENABLE 1
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c19 link->ctx->logger
38 /* to avoid infinite loop where-in the receiver
78 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
79 /* DP 1.2 or later - retrieve delay through in get_eq_training_aux_rd_interval()
113 1); in dpcd_set_training_pattern()
133 struct encoder_feature_support *features = &link->link_enc->features; in decide_eq_training_pattern()
134 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in decide_eq_training_pattern()
136 if (features->flags.bits.IS_TPS3_CAPABLE) in decide_eq_training_pattern()
139 if (features->flags.bits.IS_TPS4_CAPABLE) in decide_eq_training_pattern()
142 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && in decide_eq_training_pattern()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
82 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
84 if (!dp->force_hpd) in analogix_dp_detect_hpd()
85 return -ETIMEDOUT; in analogix_dp_detect_hpd()
92 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
97 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
98 return -EINVAL; in analogix_dp_detect_hpd()
101 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
111 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
112 if (ret != 1) { in analogix_dp_detect_sink_psr()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c85 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
87 if (!dp->force_hpd) in analogix_dp_detect_hpd()
88 return -ETIMEDOUT; in analogix_dp_detect_hpd()
95 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
100 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
101 return -EINVAL; in analogix_dp_detect_hpd()
104 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 return dp->psr_enable; in analogix_dp_psr_enabled()
120 if (!dp->psr_enable) in analogix_dp_enable_psr()
142 if (!dp->psr_enable) in analogix_dp_disable_psr()
[all …]
/kernel/linux/linux-5.10/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
45 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
150 #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
151 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
152 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/
Dserdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
57 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_serdes_pcs_get_state()
58 state->duplex = status & in mv88e6xxx_serdes_pcs_get_state()
63 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_serdes_pcs_get_state()
65 state->pause |= MLO_PAUSE_RX; in mv88e6xxx_serdes_pcs_get_state()
69 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) in mv88e6xxx_serdes_pcs_get_state()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
31 link_status[0], link_status[1], link_status[2], in intel_dp_dump_link_status()
41 int lane; in intel_get_adjust_train() local
45 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
46 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_get_adjust_train()
47 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_get_adjust_train()
63 for (lane = 0; lane < 4; lane++) in intel_get_adjust_train()
64 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train()
71 uint8_t buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
80 len = 1; in intel_dp_set_link_train()
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/
Dvideo-interfaces.txt4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
27 endpoint@1 { ... };
29 port@1 { ... };
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
[all …]
/kernel/linux/linux-4.19/drivers/net/dsa/mv88e6xxx/
Dserdes.c41 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
45 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
49 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
53 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
78 u8 cmode = chip->ports[port].cmode; in mv88e6352_port_has_serdes()
131 memcpy(data + i * ETH_GSTRING_LEN, stat->string, in mv88e6352_serdes_get_strings()
144 err = mv88e6352_serdes_read(chip, stat->reg, &reg); in mv88e6352_serdes_get_stat()
146 dev_err(chip->dev, "failed to read statistic\n"); in mv88e6352_serdes_get_stat()
152 if (stat->sizeof_stat == 32) { in mv88e6352_serdes_get_stat()
153 err = mv88e6352_serdes_read(chip, stat->reg + 1, &reg); in mv88e6352_serdes_get_stat()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
33 link_status[0], link_status[1], link_status[2], in intel_dp_dump_link_status()
58 int lane; in intel_dp_get_adjust_train() local
62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
63 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); in intel_dp_get_adjust_train()
64 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); in intel_dp_get_adjust_train()
67 preemph_max = intel_dp->preemph_max(intel_dp); in intel_dp_get_adjust_train()
68 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
77 voltage_max = intel_dp->voltage_max(intel_dp); in intel_dp_get_adjust_train()
78 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
[all …]
/kernel/linux/linux-5.10/drivers/thunderbolt/
Dlc.c1 // SPDX-License-Identifier: GPL-2.0
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
18 if (!sw->cap_lc) in tb_lc_read_uuid()
19 return -EINVAL; in tb_lc_read_uuid()
20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 if (!sw->cap_lc) in read_lc_desc()
26 return -EINVAL; in read_lc_desc()
27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc()
32 struct tb_switch *sw = port->sw; in find_port_lc_cap()
43 phys = tb_phy_port_from_link(port->port); in find_port_lc_cap()
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/omap3isp/
Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]

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