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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Dnand_ids.c31 {"TC58NVG0S3E 1G 3.3V 8-bit",
33 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
35 {"TC58NVG2S0F 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
38 {"TC58NVG2S0H 4G 3.3V 8-bit",
40 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
41 {"TC58NVG3S0F 8G 3.3V 8-bit",
43 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
44 {"TC58NVG5D2 32G 3.3V 8-bit",
46 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/mscc/
Docelot_dev.h13 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
14 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
15 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
16 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
18 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
24 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
25 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
26 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
27 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
Docelot_dev_gmii.h13 #define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_TX_RST BIT(5)
14 #define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_RX_RST BIT(4)
15 #define DEV_GMII_PORT_MODE_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_GMII_PORT_MODE_CLOCK_CFG_PHY_RST BIT(2)
22 #define DEV_GMII_PORT_MODE_PORT_MISC_MPLS_RX_ENA BIT(5)
23 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_ERROR_ENA BIT(4)
24 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_PAUSE_ENA BIT(3)
25 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_CTRL_ENA BIT(2)
26 #define DEV_GMII_PORT_MODE_PORT_MISC_GMII_LOOP_ENA BIT(1)
27 #define DEV_GMII_PORT_MODE_PORT_MISC_DEV_LOOP_ENA BIT(0)
[all …]
Docelot_hsio.h11 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
12 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
13 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
14 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
15 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
25 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
26 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
27 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
28 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
35 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/
Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/
Dtrivial-devices.txt39 dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
72 maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
73 maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
75 maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
76 mcube,mc3230 mCube 3-axis 8-bit digital accelerometer
77 memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer
78 microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k)
79 microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k)
80 microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k)
81 microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k)
[all …]
/kernel/linux/linux-4.19/drivers/net/fddi/skfp/h/
Dskfbi.h34 #define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
35 #define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
36 #define PCI_COMMAND 0x04 /* 16 bit Command */
37 #define PCI_STATUS 0x06 /* 16 bit Status */
38 #define PCI_REV_ID 0x08 /* 8 bit Revision ID */
39 #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
40 #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
41 #define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
42 #define PCI_HEADER_T 0x0e /* 8 bit Header Type */
43 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/
Dtrivial-devices.yaml109 # 5 Bit Programmable, Pulse-Width Modulator
111 # 10-bit 8 channels 300ks/s SPI ADC with temperature sensor
113 # 10-bit 12 channels 300ks/s SPI ADC with temperature sensor
115 # 10-bit 16 channels 300ks/s SPI ADC with temperature sensor
117 # 12-bit 8 channels 300ks/s SPI ADC with temperature sensor
119 # 12-bit 12 channels 300ks/s SPI ADC with temperature sensor
121 # 12-bit 16 channels 300ks/s SPI ADC with temperature sensor
123 # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
127 # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
131 # mCube 3-axis 8-bit digital accelerometer
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt76/
Dmt76x2_regs.h26 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
27 #define MT_CMB_CTRL_PLL_LD BIT(23)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
35 #define MT_EFUSE_CTRL_KICK BIT(30)
36 #define MT_EFUSE_CTRL_SEL BIT(31)
42 #define MT_COEXCFG0_COEX_EN BIT(0)
45 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
46 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
47 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
49 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-5.10/drivers/net/fddi/skfp/h/
Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
Dvc4_regs.h26 ('3' << 8) | \
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
35 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
43 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
44 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt7601u/
Dregs.h26 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
27 #define MT_CMB_CTRL_PLL_LD BIT(23)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
35 #define MT_EFUSE_CTRL_KICK BIT(30)
36 #define MT_EFUSE_CTRL_SEL BIT(31)
42 #define MT_COEXCFG0_COEX_EN BIT(0)
45 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
46 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
47 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
49 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt7601u/
Dregs.h18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
41 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
Dmac.h10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt76/mt76x0/
Dregs.h27 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
28 #define MT_CMB_CTRL_PLL_LD BIT(23)
33 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
36 #define MT_EFUSE_CTRL_KICK BIT(30)
37 #define MT_EFUSE_CTRL_SEL BIT(31)
43 #define MT_COEXCFG0_COEX_EN BIT(0)
51 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
52 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
53 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
55 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/vc4/
Dvc4_regs.h30 ('3' << 8) | \
41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
42 # define V3D_IDENT1_QUPS_SHIFT 8
51 # define V3D_L2CACTL_L2CCLR BIT(2)
52 # define V3D_L2CACTL_L2CDIS BIT(1)
53 # define V3D_L2CACTL_L2CENA BIT(0)
60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
61 # define V3D_SLCACTL_UCC_SHIFT 8
68 # define V3D_INT_SPILLUSE BIT(3)
69 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/v3d/
Dv3d_regs.h30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/marvell/
Dskge.h137 /* B0_CTST 16 bit Control/Status register */
144 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
148 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
154 /* B0_LED 8 Bit LED register */
155 /* Bit 7.. 2: reserved */
159 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
170 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
174 /* Bit 30: reserved */
201 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
221 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
195 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h19 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S)
21 #define PF_FW_ARQLEN_ARQOVFL_M BIT(PF_FW_ARQLEN_ARQOVFL_S)
23 #define PF_FW_ARQLEN_ARQCRIT_M BIT(PF_FW_ARQLEN_ARQCRIT_S)
25 #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S)
36 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S)
38 #define PF_FW_ATQLEN_ATQOVFL_M BIT(PF_FW_ATQLEN_ATQOVFL_S)
40 #define PF_FW_ATQLEN_ATQCRIT_M BIT(PF_FW_ATQLEN_ATQCRIT_S)
42 #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S)
48 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8
78 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8
[all …]

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