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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 Support Cadence DPI to DSI bridge. This is an internal
28 bridge and is meant to be directly embedded in a SoC.
44 Driver for display connectors with support for DDC and hot-plug
48 on ARM-based platforms. Saying Y here when this driver is not needed
60 Driver for Lontium LT9611 DSI to HDMI bridge
61 chip driver that converts dual DSI and I2S to
75 tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw"
82 to DP++. This is used with the i.MX6 imx-ldb
83 driver. You are likely to say N here.
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Dparade-ps8640.c1 // SPDX-License-Identifier: GPL-2.0-only
38 * page[4]: for MIPI Phy
79 struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; in ps8640_bridge_vdo_control()
87 DRM_ERROR("failed to %sable VDO: %d\n", in ps8640_bridge_vdo_control()
97 struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; in ps8640_bridge_poweron()
101 if (ps_bridge->powered) in ps8640_bridge_poweron()
104 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), in ps8640_bridge_poweron()
105 ps_bridge->supplies); in ps8640_bridge_poweron()
111 gpiod_set_value(ps_bridge->gpio_powerdown, 0); in ps8640_bridge_poweron()
112 gpiod_set_value(ps_bridge->gpio_reset, 1); in ps8640_bridge_poweron()
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Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
96 /* fudge factor required to account for 8b/10b encoding */
110 * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver.
111 * @dev: Pointer to our device.
118 * @dsi: Our MIPI DSI source.
121 * @enable_gpio: The GPIO we toggle to enable the bridge.
124 * @ln_assign: Value to program to the LN_ASSIGN register.
125 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
128 * @gchip_output: A cache of whether we've set GPIOs to output. This
129 * serves double-duty of keeping track of the direction and
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter Device Tree Bindings
10 - Nicolas Boichat <drinkcat@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
14 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 mobile devices with embedded panel resolutions up to 2048 x 1536. The
16 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
17 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
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Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Sandeep Panda <spanda@codeaurora.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
34 Set if the HPD line on the bridge isn't hooked up to anything or is
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/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_bios.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 * configuration information to the driver that is not discoverable or available
41 * through other means. The configuration is mostly related to display
50 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
51 * data. (Block 53, the MIPI Sequence Block is an exception.)
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Dintel_vbt_defs.h2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * This information is private to VBT parsing in intel_bios.c.
34 #error "intel_vbt_defs.h is private to intel_bios.c"
43 * struct vbt_header - VBT Header structure
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Dvlv_dsi.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46 /* return pixels equvalent to txbyteclkhs */
74 struct drm_encoder *encoder = &intel_dsi->base.base; in vlv_dsi_wait_for_fifo_empty()
75 struct drm_device *dev = encoder->dev; in vlv_dsi_wait_for_fifo_empty()
97 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
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Dintel_ddi.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33 u32 trans1; /* balance leg enable, de-emph level */
52 * them for both DP and FDI transports, allowing those ports to
53 * automatically adapt to HDMI connections as well
225 * eDP 1.4 low vswing translation parameters
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.txt5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
17 - phy-names: must contain "dphy"
18 - port: Output port node with endpoint definitions as described in
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.txt5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
17 - phy-names: must contain "dphy"
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_bios.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43 * configuration information to the driver that is not discoverable or available
44 * through other means. The configuration is mostly related to display
53 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
54 * data. (Block 53, the MIPI Sequence Block is an exception.)
[all …]
Dintel_vbt_defs.h2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * This information is private to VBT parsing in intel_bios.c.
34 #error "intel_vbt_defs.h is private to intel_bios.c"
43 * struct vbt_header - VBT Header structure
[all …]
Dvlv_dsi.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
50 /* return pixels equvalent to txbyteclkhs */
78 struct drm_encoder *encoder = &intel_dsi->base.base; in vlv_dsi_wait_for_fifo_empty()
79 struct drm_device *dev = encoder->dev; in vlv_dsi_wait_for_fifo_empty()
88 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/
Ddrm_dsc.c1 // SPDX-License-Identifier: MIT
22 * Compression (DSC) used to compress the pixel bits before sending it on
23 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
27 * These functions contain some common logic and helpers to deal with VESA
28 * Display Stream Compression standard required for DSC on Display Port/eDP or
29 * MIPI display interfaces.
33 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
39 * picture parameter infoframes from the source to the sink.
47 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
48 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.txt4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
13 - "aotag"
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/kernel/linux/linux-5.10/Documentation/userspace-api/media/mediactl/
Dmedia-types.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-types:
5 Types and flags used to represent the media graph elements
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
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/kernel/linux/linux-4.19/Documentation/media/uapi/mediactl/
Dmedia-types.rst1 .. -*- coding: utf-8; mode: rst -*-
3 .. _media-controller-types:
5 Types and flags used to represent the media graph elements
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/sunxi/
Dsun4i-drm.txt5 that are going to be documented below:
7 For all connections between components up to the TCONs in the display
13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
14 [1] -- -- [1] [1] -- -- [1]
18 [0] -- -- [0] [0] -- -- [0]
19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
23 within the square brackets corresponds to the ID of the local endpoint.
25 The same rule also applies to DE 2.0 mixer-TCON connections:
27 Mixer 0 [0] ----------- [0] TCON 0
28 [1] ---- ---- [1]
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/power/rk3288-power.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
30 * For now we can just model it as a multiplier clock, and force P to /1.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
64 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
[all …]
/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c2 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
14 #include <linux/clk-provider.h>
28 #include "ccu-sun9i-a80.h"
35 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
37 * For now we can just model it as a multiplier clock, and force P to /1.
50 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
64 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
71 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
86 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
102 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]

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