| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-pxa.txt | 1 * Marvell sdhci-pxa v2/v3 controller
4 and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
7 - compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
8 "marvell,armada-380-sdhci".
9 - reg:
10 * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
13 * for "marvell,armada-380-sdhci", three register areas. The first
17 - reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory
18 for "marvell,armada-380-sdhci"
19 - clocks: Array of clocks required for SDHCI; requires at least one for
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-pxa.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
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| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | gpmc-omap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
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| /kernel/linux/linux-4.19/include/linux/platform_data/ |
| D | gpmc-omap.h | 4 * Copyright (C) 2014 Texas Instruments, Inc. - http://www.ti.com
31 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
37 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
61 u32 page_burst_access; /* Multiple access word delay */
62 u32 access; /* Start-cycle to first data valid delay */
107 u32 clk; member
108 u32 t_bacc; /* burst access valid clock to output delay */
109 u32 t_ces; /* CS setup time to clk */
110 u32 t_avds; /* ADV setup time to clk */
111 u32 t_avdh; /* ADV hold time from clk */
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | pl172.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
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| /kernel/linux/linux-4.19/drivers/memory/ |
| D | pl172.c | 8 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
16 #include <linux/clk.h>
56 struct clk *clk; member
64 int cycles; in pl172_timing_prop() local
68 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 if (cycles < 0) { in pl172_timing_prop()
70 cycles = 0; in pl172_timing_prop()
71 } else if (cycles > max) { in pl172_timing_prop()
72 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
73 return -EINVAL; in pl172_timing_prop()
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | renesas_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
10 #include <linux/delay.h>
36 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
38 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
39 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
62 writel_relaxed(val, priv->base + reg); in rwdt_write()
69 rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); in rwdt_init_timeout()
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| D | imgpdc_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
18 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21 * as a power of two number of watchdog clock cycles. The current implementation
25 * The following table shows how the user-configured timeout relates
29 * -----------------------------------
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
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| /kernel/linux/linux-4.19/drivers/clocksource/ |
| D | tegra20_timer.c | 25 #include <linux/clk.h>
30 #include <linux/delay.h>
64 static int tegra_timer_set_next_event(unsigned long cycles, in tegra_timer_set_next_event() argument
69 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); in tegra_timer_set_next_event()
88 u32 reg = 0xC0000000 | ((1000000 / HZ) - 1); in tegra_timer_set_periodic()
114 * tegra_rtc_read - Reads the Tegra RTC registers
127 * tegra_read_persistent_clock64 - Return time from a persistent clock.
130 * 32k sync timer. Convert the cycles elapsed since last read into
142 delta = persistent_ms - last_persistent_ms; in tegra_read_persistent_clock64()
157 evt->event_handler(evt); in tegra_timer_interrupt()
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| D | timer-fttmr010.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
76 * - aspeed timer overflow interrupt is controlled by bits in Control
78 * - aspeed timers always generate interrupt when either one of the
106 * A local singleton used by sched_clock and delay timer reads, which are
118 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
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| D | timer-sun5i.c | 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
13 #include <linux/clk.h>
16 #include <linux/delay.h>
43 struct clk *clk; member
68 * When we disable a timer, we need to wait at least for 2 cycles of
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
84 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
89 static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay) in sun5i_clkevt_time_setup() argument
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| /kernel/linux/linux-4.19/drivers/pwm/ |
| D | pwm-atmel.c | 10 #include <linux/clk.h>
11 #include <linux/delay.h>
70 struct clk *clk; member
87 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
93 writel_relaxed(val, chip->base + offset); in atmel_pwm_writel()
101 return readl_relaxed(chip->base + base + offset); in atmel_pwm_ch_readl()
110 writel_relaxed(val, chip->base + base + offset); in atmel_pwm_ch_writel()
118 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres() local
120 /* Calculate the period cycles and prescale value */ in atmel_pwm_calculate_cprd_and_pres()
121 cycles *= clk_get_rate(atmel_pwm->clk); in atmel_pwm_calculate_cprd_and_pres()
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| /kernel/linux/linux-5.10/drivers/char/hw_random/ |
| D | ks-sa-rng.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
16 #include <linux/clk.h>
23 #include <linux/delay.h>
64 /* Number of CLK input cycles between samples */
70 /* Delay between retries (in usecs) */
86 struct clk *clk; member
93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
116 struct device *dev = (struct device *)rng->priv; in ks_sa_rng_init()
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | tegra194-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp-abi.h>
47 u32 delay; member
67 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
97 * ref_clk_counter(32 bit counter) runs on constant clk, in tegra_read_counters()
99 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
105 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
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| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-atmel.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
23 #include <linux/delay.h>
83 struct clk *clk; member
100 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
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| /kernel/linux/linux-4.19/drivers/clk/mmp/ |
| D | clk-gate.c | 12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
18 #include "clk.h"
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
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| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-gate.c | 12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
18 #include "clk.h"
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
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| /kernel/linux/linux-4.19/drivers/watchdog/ |
| D | imgpdc_wdt.c | 14 * -----
15 * The timeout value is rounded to the next power of two clock cycles.
19 * timeout = 2^(delay + 1) clock cycles
21 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
24 * as a power of two number of watchdog clock cycles. The current implementation
28 * The following table shows how the user-configured timeout relates
32 * -----------------------------------
43 #include <linux/clk.h>
87 struct clk *wdt_clk;
88 struct clk *sys_clk;
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| /kernel/linux/linux-5.10/drivers/iio/adc/ |
| D | cc10001_adc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
6 #include <linux/clk.h>
7 #include <linux/delay.h>
48 * As per device specification, wait six clock cycles after power-up to
49 * activate START. Since adding two more clock cycles delay does not
50 * impact the performance too much, we are adding two additional cycles delay
57 struct clk *adc_clk;
70 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
76 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | mmp2-olpc-xo-1-75.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "OLPC XO-1.75";
16 compatible = "olpc,xo-1.75", "mrvl,mmp2";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "simple-framebuffer";
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-fttmr010.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
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| D | timer-imx-tpm.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk.h>
9 #include <linux/delay.h>
13 #include "timer-of.h"
95 * contention between GPU and A7 may results a few cycles delay in tpm_set_next_event()
99 return (int)(next - now) <= 0 ? -ETIME : 0; in tpm_set_next_event()
122 evt->event_handler(evt); in tpm_timer_interrupt()
159 "imx-tpm", in tpm_clocksource_init()
171 GENMASK(counter_width - 1, in tpm_clockevent_init()
177 struct clk *ipg; in tpm_timer_init()
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| /kernel/linux/linux-4.19/drivers/iio/adc/ |
| D | cc10001_adc.c | 2 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
52 * As per device specification, wait six clock cycles after power-up to
53 * activate START. Since adding two more clock cycles delay does not
54 * impact the performance too much, we are adding two additional cycles delay
61 struct clk *adc_clk;
74 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
80 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
86 ndelay(adc_dev->start_delay_ns); in cc10001_adc_power_up()
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| /kernel/linux/linux-5.10/drivers/nvmem/ |
| D | mxs-ocotp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
9 #include <linux/clk.h>
10 #include <linux/delay.h>
15 #include <linux/nvmem-provider.h>
31 struct clk *clk; member
41 while (timeout--) { in mxs_ocotp_wait()
42 status = readl(otp->base); in mxs_ocotp_wait()
51 return -EBUSY; in mxs_ocotp_wait()
53 return -EIO; in mxs_ocotp_wait()
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| /kernel/linux/linux-4.19/drivers/nvmem/ |
| D | mxs-ocotp.c | 2 * Freescale MXS On-Chip OTP driver
19 #include <linux/clk.h>
20 #include <linux/delay.h>
25 #include <linux/nvmem-provider.h>
41 struct clk *clk; member
51 while (timeout--) { in mxs_ocotp_wait()
52 status = readl(otp->base); in mxs_ocotp_wait()
61 return -EBUSY; in mxs_ocotp_wait()
63 return -EIO; in mxs_ocotp_wait()
75 ret = clk_enable(otp->clk); in mxs_ocotp_read()
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