| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
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| D | mtk-sd.txt | 10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
18 "mediatek,mt7622-mmc": for MT7622 SoC
19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
[all …]
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| D | exynos-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
27 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.txt | 9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
21 interface and timing delay.
[all …]
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| D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
6 clock support is added to the kernel.
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
6 clock support is added to the kernel.
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/spi/ |
| D | sh-msiof.txt | 4 - compatible : "renesas,msiof-r8a7743" (RZ/G1M)
5 "renesas,msiof-r8a7745" (RZ/G1E)
6 "renesas,msiof-r8a7790" (R-Car H2)
7 "renesas,msiof-r8a7791" (R-Car M2-W)
8 "renesas,msiof-r8a7792" (R-Car V2H)
9 "renesas,msiof-r8a7793" (R-Car M2-N)
10 "renesas,msiof-r8a7794" (R-Car E2)
11 "renesas,msiof-r8a7795" (R-Car H3)
12 "renesas,msiof-r8a7796" (R-Car M3-W)
13 "renesas,msiof-r8a77965" (R-Car M3-N)
[all …]
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| D | spi-fsl-dspi.txt | 4 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
5 "fsl,ls2085a-dspi"
7 "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8 "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
9 - reg : Offset and length of the register set for the device
10 - interrupts : Should contain SPI controller interrupt
11 - clocks: from common clock binding: handle to dspi clock.
12 - clock-names: from common clock binding: Shall be "dspi".
13 - pinctrl-0: pin control group to be used for this controller.
14 - pinctrl-names: must contain a "default" entry.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.txt | 10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
14 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
15 "mediatek,mt7622-mmc": for MT7622 SoC
16 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
18 - reg: physical base address of the controller and length
19 - interrupts: Should contain MSDC interrupt number
20 - clocks: Should contain phandle for the clock feeding the MMC controller
[all …]
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| D | sdhci-cadence.txt | 4 - compatible: should be one of the following:
5 "cdns,sd4hc" - default of the IP
6 "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs
7 - reg: offset and length of the register set for the device.
8 - interrupts: a single interrupt specifier.
9 - clocks: phandle to the input clock.
15 - mmc-ddr-1_8v
16 - mmc-ddr-1_2v
17 - mmc-hs200-1_8v
18 - mmc-hs200-1_2v
[all …]
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| D | exynos-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
27 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | rt5682.txt | 7 - compatible : "realtek,rt5682" or "realtek,rt5682i"
9 - reg : The I2C address of the device.
13 - interrupts : The CODEC's interrupt output.
15 - realtek,dmic1-data-pin
20 - realtek,dmic1-clk-pin
21 0: using GPIO1 pin as dmic1 clock pin
22 1: using GPIO3 pin as dmic1 clock pin
24 - realtek,jd-src
28 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
30 - realtek,btndet-delay
[all …]
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| /kernel/linux/linux-4.19/Documentation/timers/ |
| D | timekeeping.txt | 1 Clock sources, Clock events, sched_clock() and delay timers
2 -----------------------------------------------------------
9 If you grep through the kernel source you will find a number of architecture-
10 specific implementations of clock sources, clockevents and several likewise
11 architecture-specific overrides of the sched_clock() function and some
12 delay timers.
14 To provide timekeeping for your platform, the clock source provides
15 the basic timeline, whereas clock events shoot interrupts on certain points
16 on this timeline, providing facilities such as high-resolution timers.
17 sched_clock() is used for scheduling and timestamping, and delay timers
[all …]
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| /kernel/linux/linux-5.10/Documentation/timers/ |
| D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
13 delay timers.
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
18 sched_clock() is used for scheduling and timestamping, and delay timers
19 provide an accurate delay source using hardware counters.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
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| D | spi-fsl-dspi.txt | 4 - compatible : must be one of:
5 "fsl,vf610-dspi",
6 "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
8 "fsl,ls1028a-dspi",
9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
13 "fsl,ls2085a-dspi",
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | meson-dwmac.txt | 9 - compatible: Depending on the platform this should be one of:
10 - "amlogic,meson6-dwmac"
11 - "amlogic,meson8b-dwmac"
12 - "amlogic,meson8m2-dwmac"
13 - "amlogic,meson-gxbb-dwmac"
14 - "amlogic,meson-axg-dwmac"
19 - reg: The first register range should be the one of the DWMAC
25 - clock-names: Should contain the following:
26 - "stmmaceth" - see stmmac.txt
27 - "clkin0" - first parent clock of the internal mux
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | msm8998.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
16 #address-cells = <2>;
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
20 u8 delay; in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
26 if (!delay) in ccu_phase_get_phase()
29 /* Get our parent clock, it's the one that can adjust its rate */ in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 3 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/clk-provider.h>
23 u8 delay; in ccu_phase_get_phase() local
25 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
26 delay = (reg >> phase->shift); in ccu_phase_get_phase()
27 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
29 if (!delay) in ccu_phase_get_phase()
32 /* Get our parent clock, it's the one that can adjust its rate */ in ccu_phase_get_phase()
35 return -EINVAL; in ccu_phase_get_phase()
40 return -EINVAL; in ccu_phase_get_phase()
[all …]
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| /kernel/linux/linux-5.10/include/linux/amba/ |
| D | pl022.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
30 * enum ssp_interface - interfaces allowed for this SSP Controller
47 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
55 * enum ssp_clock_params - clock parameters, to set SSP clock at a
64 * enum ssp_rx_endian - endianess of Rx FIFO Data
73 * enum ssp_tx_endian - endianess of Tx FIFO Data
81 * enum ssp_data_size - number of bits in one data element
97 * enum ssp_mode - SSP mode of operation (Communication modes)
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 - reg : Contains two entries, each of which is a tuple consisting of a
11 - interrupts : Unit interrupt specifier for the controller interrupt.
12 - clocks : phandle to the Quad SPI clock.
13 - cdns,fifo-depth : Size of the data FIFO in words.
14 - cdns,fifo-width : Bus width of the data FIFO in bytes.
15 - cdns,trigger-address : 32-bit indirect AHB trigger address.
18 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
[all …]
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