| /kernel/linux/linux-5.10/drivers/usb/dwc3/ |
| D | Makefile | 5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
46 obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
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| D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
73 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
[all …]
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| D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer
56 * @dwc3: child dwc3 platform_device
63 struct platform_device *dwc3; member
212 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
215 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
217 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
221 pm_runtime_mark_last_busy(&dwc3->dev); in dwc3_pci_resume_work()
222 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
246 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
247 if (!dwc->dwc3) in dwc3_pci_probe()
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| D | core.c | 47 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap()
117 static int dwc3_core_soft_reset(struct dwc3 *dwc);
121 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
247 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
263 static int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
270 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
316 * @dwc3: Pointer to our controller context structure
[all …]
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| /kernel/linux/linux-4.19/drivers/usb/dwc3/ |
| D | Makefile | 5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
46 obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
[all …]
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| D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
73 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
[all …]
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| D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer
51 * @dwc3: child dwc3 platform_device
58 struct platform_device *dwc3; member
203 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
206 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
208 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
212 pm_runtime_mark_last_busy(&dwc3->dev); in dwc3_pci_resume_work()
213 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
237 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
238 if (!dwc->dwc3) in dwc3_pci_probe()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/dwc3.txt
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
[all …]
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| D | dwc3.txt | 1 synopsys DWC3 CORE
3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
9 - interrupts: Interrupts used by the dwc3 controller.
17 "amlogic,meson-axg-dwc3"
18 "amlogic,meson-gxl-dwc3"
20 "qcom,dwc3"
23 "sprd,sc9860-dwc3"
24 "st,stih407-dwc3"
25 "ti,am437x-dwc3"
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| D | keystone-usb.txt | 3 DWC3 GLUE
6 - compatible: should be "ti,keystone-dwc3".
32 The dwc3 core should be added as subnode to Keystone DWC3 glue.
33 - dwc3 :
34 The binding details of dwc3 can be found in:
35 Documentation/devicetree/bindings/usb/dwc3.txt
39 compatible = "ti,keystone-dwc3";
48 dwc3@2690000 {
49 compatible = "synopsys,dwc3";
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| D | amlogic,dwc3.txt | 1 Amlogic Meson GX DWC3 USB SoC controller
5 * amlogic,meson-axg-dwc3
6 * amlogic,meson-gxl-dwc3
13 A child node must exist to represent the core DWC3 IP block. The name of
14 the node is not important. The content of the node is defined in dwc3.txt.
22 compatible = "amlogic,meson-axg-dwc3";
32 dwc3: dwc3@ff500000 {
33 compatible = "snps,dwc3";
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| D | rockchip,dwc3.txt | 1 Rockchip SuperSpeed DWC3 USB SoC controller
4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
15 A child node must exist to represent the core DWC3 IP block. The name of
16 the node is not important. The content of the node is defined in dwc3.txt.
25 compatible = "rockchip,rk3399-dwc3";
33 usbdrd_dwc3_0: dwc3@fe800000 {
34 compatible = "snps,dwc3";
42 compatible = "rockchip,rk3399-dwc3";
50 usbdrd_dwc3_1: dwc3@fe900000 {
51 compatible = "snps,dwc3";
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| D | qcom,dwc3.txt | 1 Qualcomm SuperSpeed DWC3 USB SoC controller
5 "qcom,dwc3"
6 "qcom,msm8996-dwc3" for msm8996 SOC.
7 "qcom,sdm845-dwc3" for sdm845 SOC.
22 Not present on "qcom,msm8996-dwc3" compatible.
24 Not present on "qcom,msm8996-dwc3" compatible.
46 Used when dwc3 operates without SSPHY and only
50 A child node must exist to represent the core DWC3 IP block. The name of
51 the node is not important. The content of the node is defined in dwc3.txt.
70 compatible = "qcom,dwc3";
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| D | omap-usb.txt | 46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/dwc3.txt
71 compatible = "ti,dwc3";
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| D | dwc3-xilinx.txt | 1 Xilinx SuperSpeed DWC3 USB SoC controller
4 - compatible: Should contain "xlnx,zynqmp-dwc3"
13 A child node must exist to represent the core DWC3 IP block. The name of
14 the node is not important. The content of the node is defined in dwc3.txt.
21 compatible = "xlnx,zynqmp-dwc3";
26 dwc3@fe200000 {
27 compatible = "snps,dwc3";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/dwc3.txt
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
[all …]
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| D | qcom,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
19 - qcom,sdm845-dwc3
20 - const: qcom,dwc3
99 Used when dwc3 operates without SSPHY and only
106 "^dwc3@[0-9a-f]+$":
109 A child node must exist to represent the core DWC3 IP block
[all …]
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| D | rockchip,dwc3.txt | 1 Rockchip SuperSpeed DWC3 USB SoC controller
4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
15 A child node must exist to represent the core DWC3 IP block. The name of
16 the node is not important. The content of the node is defined in dwc3.txt.
25 compatible = "rockchip,rk3399-dwc3";
33 usbdrd_dwc3_0: dwc3@fe800000 {
34 compatible = "snps,dwc3";
42 compatible = "rockchip,rk3399-dwc3";
50 usbdrd_dwc3_1: dwc3@fe900000 {
51 compatible = "snps,dwc3";
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| D | dwc3.txt | 1 synopsys DWC3 CORE
3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
9 - interrupts: Interrupts used by the dwc3 controller.
19 "qcom,dwc3"
23 "sprd,sc9860-dwc3"
24 "st,stih407-dwc3"
25 "ti,am437x-dwc3"
26 "ti,dwc3"
27 "ti,keystone-dwc3"
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| D | intel,keembay-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
37 "^dwc3@[0-9a-f]+$":
40 A child node must exist to represent the core DWC3 IP block.
41 The content of the node is defined in dwc3.txt.
61 compatible = "intel,keembay-dwc3";
71 dwc3@34000000 {
72 compatible = "snps,dwc3";
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| D | omap-usb.txt | 46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/dwc3.txt
71 compatible = "ti,dwc3";
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| D | exynos-usb.txt | 68 DWC3
71 "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
73 "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
75 "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
93 The dwc3 core should be added as subnode to Exynos dwc3 glue.
94 - dwc3 :
95 The binding details of dwc3 can be found in:
96 Documentation/devicetree/bindings/usb/dwc3.txt
109 dwc3 {
110 compatible = "synopsys,dwc3";
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| D | dwc3-xilinx.txt | 1 Xilinx SuperSpeed DWC3 USB SoC controller
4 - compatible: Should contain "xlnx,zynqmp-dwc3"
13 A child node must exist to represent the core DWC3 IP block. The name of
14 the node is not important. The content of the node is defined in dwc3.txt.
21 compatible = "xlnx,zynqmp-dwc3";
26 dwc3@fe200000 {
27 compatible = "snps,dwc3";
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| D | ti,keystone-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
68 description: This is the node representing the DWC3 controller instance
69 Documentation/devicetree/bindings/usb/dwc3.txt
85 dwc3@2680000 {
86 compatible = "ti,keystone-dwc3";
95 compatible = "synopsys,dwc3";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | qcom-dwc3-usb-phy.txt | 1 Qualcomm DWC3 HS AND SS PHY CONTROLLER
4 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
5 controllers. Each DWC3 PHY controller should have its own node.
9 - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
10 - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
11 - reg: offset and length of the DWC3 PHY controller register set
22 compatible = "qcom,dwc3-hs-usb-phy";
31 compatible = "qcom,dwc3-ss-usb-phy";
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