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/third_party/uboot/u-boot-2020.01/arch/mips/mach-ath79/include/mach/
Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
361 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
387 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
388 #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
400 #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30)
401 #define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
403 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
404 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
405 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
[all …]
/third_party/uboot/u-boot-2020.01/arch/mips/mach-jz47xx/jz4780/
Dtimer.c42 #define TCU_TCSR_PWM_SD BIT(9)
43 #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
44 #define TCU_TCSR_PWM_EN BIT(7)
53 #define TCU_TCSR_EXT_EN BIT(2)
54 #define TCU_TCSR_RTC_EN BIT(1)
55 #define TCU_TCSR_PCK_EN BIT(0)
57 #define TCU_TER_TCEN5 BIT(5)
58 #define TCU_TER_TCEN4 BIT(4)
59 #define TCU_TER_TCEN3 BIT(3)
60 #define TCU_TER_TCEN2 BIT(2)
[all …]
Dpll.c85 #define CPM_CPCSR_H2DIV_BUSY BIT(2)
86 #define CPM_CPCSR_H0DIV_BUSY BIT(1)
87 #define CPM_CPCSR_CDIV_BUSY BIT(0)
100 #define CPM_CPXPCR_XLOCK BIT(6)
101 #define CPM_CPXPCR_XPLL_ON BIT(4)
102 #define CPM_CPXPCR_XF_MODE BIT(3)
103 #define CPM_CPXPCR_XPLLBP BIT(1)
104 #define CPM_CPXPCR_XPLLEN BIT(0)
111 #define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/
112 #define CPM_USBPCR_AVLD_REG BIT(30)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/sound/
Dmax98090.h71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
79 #define M98090_SR_32K_MASK BIT(4)
82 #define M98090_SR_48K_MASK BIT(3)
85 #define M98090_SR_44K1_MASK BIT(2)
88 #define M98090_SR_16K_MASK BIT(1)
91 #define M98090_SR_8K_MASK BIT(0)
97 #define M98090_SR_ALL_NUM BIT(M98090_SR_ALL_WIDTH)
102 #define M98090_RJ_M_MASK BIT(5)
105 #define M98090_RJ_S_MASK BIT(4)
[all …]
Dmax98088.h97 #define M98088_DAI_MAS BIT(7)
98 #define M98088_DAI_WCI BIT(6)
99 #define M98088_DAI_BCI BIT(5)
100 #define M98088_DAI_DLY BIT(4)
101 #define M98088_DAI_TDM BIT(2)
102 #define M98088_DAI_FSW BIT(1)
103 #define M98088_DAI_WS BIT(0)
106 #define M98088_DAI_BSEL64 BIT(0)
107 #define M98088_DAI_OSR64 BIT(6)
110 #define M98088_S1NORMAL BIT(6)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/net/
Dftgmac100.h73 #define FTGMAC100_INT_RPKT_BUF BIT(0)
74 #define FTGMAC100_INT_RPKT_FIFO BIT(1)
75 #define FTGMAC100_INT_NO_RXBUF BIT(2)
76 #define FTGMAC100_INT_RPKT_LOST BIT(3)
77 #define FTGMAC100_INT_XPKT_ETH BIT(4)
78 #define FTGMAC100_INT_XPKT_FIFO BIT(5)
79 #define FTGMAC100_INT_NO_NPTXBUF BIT(6)
80 #define FTGMAC100_INT_XPKT_LOST BIT(7)
81 #define FTGMAC100_INT_AHB_ERR BIT(8)
82 #define FTGMAC100_INT_PHYSTS_CHG BIT(9)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/clk/sunxi/
Dclk_r40.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
[all …]
Dclk_a31.c16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
24 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
25 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
[all …]
Dclk_h3.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
[all …]
Dclk_h6.c16 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
17 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
18 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
19 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
20 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
21 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
22 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
24 [CLK_SPI0] = GATE(0x940, BIT(31)),
25 [CLK_SPI1] = GATE(0x944, BIT(31)),
27 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
[all …]
Dclk_a64.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[all …]
Dclk_a83t.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
[all …]
Dclk_a23.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
23 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
25 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
26 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[all …]
/third_party/libphonenumber/resources/carrier/en/
D370.txt18 37063|BITÄ
19 37064|BITÄ
24 37065|BITÄ
25 370660|BITÄ
26 370661|BITÄ
29 37066313|BITÄ
30 37066314|BITÄ
31 37066315|BITÄ
32 37066316|BITÄ
33 37066317|BITÄ
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/include/mach/
Dreset_manager_arria10.h79 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
80 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
81 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
82 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
83 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
84 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
85 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
86 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
87 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
88 #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/mmc/
Dtmio-common.h11 #define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
12 #define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
13 #define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
14 #define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
15 #define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
24 #define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
25 #define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
32 #define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
33 #define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
34 #define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
[all …]
/third_party/uboot/u-boot-2020.01/include/net/pfe_eth/pfe/cbus/
Demac.h32 #define EMAC_IEVENT_HBERR BIT(31)
33 #define EMAC_IEVENT_BABR BIT(30)
34 #define EMAC_IEVENT_BABT BIT(29)
35 #define EMAC_IEVENT_GRA BIT(28)
36 #define EMAC_IEVENT_TXF BIT(27)
37 #define EMAC_IEVENT_TXB BIT(26)
38 #define EMAC_IEVENT_RXF BIT(25)
39 #define EMAC_IEVENT_RXB BIT(24)
40 #define EMAC_IEVENT_MII BIT(23)
41 #define EMAC_IEVENT_EBERR BIT(22)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/usb/cdns3/
Dgadget.h124 #define USB_CONF_CFGRST BIT(0)
126 #define USB_CONF_CFGSET BIT(1)
128 #define USB_CONF_USB3DIS BIT(3)
130 #define USB_CONF_USB2DIS BIT(4)
132 #define USB_CONF_LENDIAN BIT(5)
138 #define USB_CONF_BENDIAN BIT(6)
140 #define USB_CONF_SWRST BIT(7)
142 #define USB_CONF_DSING BIT(8)
144 #define USB_CONF_DMULT BIT(9)
146 #define USB_CONF_DMAOFFEN BIT(10)
[all …]
/third_party/wpa_supplicant/wpa_supplicant-2.9/src/common/
Dieee802_11_defs.h32 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
34 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
91 #define WLAN_CAPABILITY_ESS BIT(0)
92 #define WLAN_CAPABILITY_IBSS BIT(1)
93 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
94 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
95 #define WLAN_CAPABILITY_PRIVACY BIT(4)
96 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
97 #define WLAN_CAPABILITY_PBCC BIT(6)
98 #define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7)
[all …]
Ddefs.h21 #define WPA_CIPHER_NONE BIT(0)
22 #define WPA_CIPHER_WEP40 BIT(1)
23 #define WPA_CIPHER_WEP104 BIT(2)
24 #define WPA_CIPHER_TKIP BIT(3)
25 #define WPA_CIPHER_CCMP BIT(4)
26 #define WPA_CIPHER_AES_128_CMAC BIT(5)
27 #define WPA_CIPHER_GCMP BIT(6)
28 #define WPA_CIPHER_SMS4 BIT(7)
29 #define WPA_CIPHER_GCMP_256 BIT(8)
30 #define WPA_CIPHER_CCMP_256 BIT(9)
[all …]
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/common/
Dieee802_11_defs.h32 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
34 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
91 #define WLAN_CAPABILITY_ESS BIT(0)
92 #define WLAN_CAPABILITY_IBSS BIT(1)
93 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
94 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
95 #define WLAN_CAPABILITY_PRIVACY BIT(4)
96 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
97 #define WLAN_CAPABILITY_PBCC BIT(6)
98 #define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7)
[all …]
Ddefs.h21 #define WPA_CIPHER_NONE BIT(0)
22 #define WPA_CIPHER_WEP40 BIT(1)
23 #define WPA_CIPHER_WEP104 BIT(2)
24 #define WPA_CIPHER_TKIP BIT(3)
25 #define WPA_CIPHER_CCMP BIT(4)
26 #define WPA_CIPHER_AES_128_CMAC BIT(5)
27 #define WPA_CIPHER_GCMP BIT(6)
28 #define WPA_CIPHER_SMS4 BIT(7)
29 #define WPA_CIPHER_GCMP_256 BIT(8)
30 #define WPA_CIPHER_CCMP_256 BIT(9)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/phy/marvell/
Dcomphy_a3700.h27 #define rb_pin_pu_iveref BIT(1)
28 #define rb_pin_reset_core BIT(11)
29 #define rb_pin_reset_comphy BIT(12)
30 #define rb_pin_pu_pll BIT(16)
31 #define rb_pin_pu_rx BIT(17)
32 #define rb_pin_pu_tx BIT(18)
33 #define rb_pin_tx_idle BIT(19)
38 #define rb_phy_rx_init BIT(30)
41 #define rb_rx_init_done BIT(0)
42 #define rb_pll_ready_rx BIT(2)
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-rockchip/
Dlvds_rk3288.h10 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
11 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
12 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
13 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
14 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
15 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
16 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
17 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
20 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
21 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
[all …]
/third_party/uboot/u-boot-2020.01/drivers/reset/
Dreset-imx7.c35 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
36 [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
37 [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
38 [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
39 [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
40 [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
41 [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
42 [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
43 [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
44 [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
[all …]

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