| /third_party/uboot/u-boot-2020.01/board/freescale/mpc832xemds/ |
| D | pci.c | 28 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
75 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
133 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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| /third_party/uboot/u-boot-2020.01/board/sbc8349/ |
| D | pci.c | 28 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
63 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8349emds/ |
| D | pci.c | 24 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
139 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
163 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
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| /third_party/uboot/u-boot-2020.01/board/xes/xpedite520x/ |
| D | tlb.c | 62 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
|
| /third_party/uboot/u-boot-2020.01/board/tqc/tqm834x/ |
| D | pci.c | 26 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
91 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8349itx/ |
| D | pci.c | 25 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
93 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/board/esd/vme8349/ |
| D | pci.c | 32 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
102 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8313erdb/ |
| D | mpc8313erdb.c | 70 .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
92 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/include/configs/ |
| D | MPC8610HPCD.h | 229 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 macro
306 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
309 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
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| D | MPC8349ITX.h | 282 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 macro
296 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
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| D | MPC8548CDS.h | 337 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull macro
339 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 macro
|
| D | MPC8536DS.h | 388 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull macro
390 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 macro
|
| D | TQM834x.h | 169 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE macro
|
| D | socrates.h | 164 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE macro
|
| D | caddy2.h | 145 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 macro
|
| D | MPC832XEMDS.h | 189 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 macro
|
| D | vme8349.h | 145 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 macro
|
| D | ve8313.h | 172 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 macro
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8323erdb/ |
| D | mpc8323erdb.c | 156 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
176 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8541cds/ |
| D | law.c | 35 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8555cds/ |
| D | law.c | 35 SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
|
| /third_party/uboot/u-boot-2020.01/board/ve8313/ |
| D | ve8313.c | 167 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
189 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); in pci_init_board()
|
| /third_party/uboot/u-boot-2020.01/arch/powerpc/cpu/mpc85xx/ |
| D | pci.c | 91 pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; in pci_mpc85xx_init()
114 CONFIG_SYS_PCI1_IO_PHYS, in pci_mpc85xx_init()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8548cds/ |
| D | tlb.c | 73 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8536ds/ |
| D | tlb.c | 49 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
|