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Searched refs:DDR_PHY_DVRFTCTRL (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_t16.h42 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ macro
336 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \
341 base_phy + DDR_PHY_DVRFTCTRL); \
353 base_phy + DDR_PHY_DVRFTCTRL); \
Dddr_phy_t28.h41 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ macro
334 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \
339 base_phy + DDR_PHY_DVRFTCTRL); \
351 base_phy + DDR_PHY_DVRFTCTRL); \
Dddr_phy_s28_v300.h44 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ macro
368 ddr_read((base_phy) + DDR_PHY_DVRFTCTRL); \
373 (base_phy) + DDR_PHY_DVRFTCTRL); \
385 (base_phy) + DDR_PHY_DVRFTCTRL); \
Dddr_phy_t12_v101.h44 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ macro
363 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \
368 base_phy + DDR_PHY_DVRFTCTRL); \
380 base_phy + DDR_PHY_DVRFTCTRL); \
Dddr_phy_t12_v100.h44 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ macro
364 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \
369 base_phy + DDR_PHY_DVRFTCTRL); \
381 base_phy + DDR_PHY_DVRFTCTRL); \
Dddr_phy_s40.h37 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ macro
Dddr_training_impl.c1635 unsigned int dvrft_ctrl = ddr_read(base_phy + DDR_PHY_DVRFTCTRL); in ddr_hw_training_ctl()
1689 base_phy + DDR_PHY_DVRFTCTRL); in ddr_hw_training_ctl()
1702 ddr_write(dvrft_ctrl, base_phy + DDR_PHY_DVRFTCTRL); in ddr_hw_training_ctl()