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Searched refs:DDR_PHY_DXNRDQNBDL1 (Results 1 – 9 of 9) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_cmd_ctl.c113 {0, 0, DDR_PHY_DXNRDQNBDL1(0, 0), 0, "RDQ BDL DQ4-DQ7"},
115 {0, 1, DDR_PHY_DXNRDQNBDL1(0, 1), 0, "RDQ BDL DQ12-DQ15"},
117 {0, 2, DDR_PHY_DXNRDQNBDL1(0, 2), 0, "RDQ BDL DQ20-DQ23"},
119 {0, 3, DDR_PHY_DXNRDQNBDL1(0, 3), 0, "RDQ BDL DQ28-DQ31"},
167 {1, 0, DDR_PHY_DXNRDQNBDL1(1, 0), 0, "RDQ BDL DQ4-DQ7"},
169 {1, 1, DDR_PHY_DXNRDQNBDL1(1, 1), 0, "RDQ BDL DQ12-DQ15"},
171 {1, 2, DDR_PHY_DXNRDQNBDL1(1, 2), 0, "RDQ BDL DQ20-DQ23"},
173 {1, 3, DDR_PHY_DXNRDQNBDL1(1, 3), 0, "RDQ BDL DQ28-DQ31"},
Dddr_training_impl.c546 offset = DDR_PHY_DXNRDQNBDL1(rank, byte_index); in ddr_phy_set_dq_bdl()
577 offset = DDR_PHY_DXNRDQNBDL1(rank, byte_index); in ddr_phy_get_dq_bdl()
632 cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte), in ddr_rdqs_sync_rank_rdq()
633 ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte)), offset); in ddr_rdqs_sync_rank_rdq()
648 cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte), in ddr_rdqs_sync_rank_rdq()
649 ddr_read(cfg->cur_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, cfg->cur_byte))); in ddr_rdqs_sync_rank_rdq()
664 dq47 = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_idx)); in ddr_bdl_adj()
692 ddr_write(dq47, base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_idx)); in ddr_bdl_adj()
917 dq4_7 = ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, byte_index)); in ddr_adjust_get_average()
1494 ddr_write(ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, i)) in ddr_hw_read_adj()
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Dddr_phy_s40.h58 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t16.h68 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t28.h67 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_s28_v300.h71 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t12_v101.h62 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t12_v100.h62 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) macro
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/cmd_bin/
Dddr_training_cmd.c325 base_phy + DDR_PHY_DXNRDQNBDL1(rank, i), in dump_result()
326 ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, i)), in dump_result()