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Searched refs:DDR_PHY_DXNRDQSGDLY (Results 1 – 9 of 9) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_cmd_ctl.c120 {0, 0, DDR_PHY_DXNRDQSGDLY(0, 0), 0, "Gate Byte0"},
121 {0, 1, DDR_PHY_DXNRDQSGDLY(0, 1), 0, "Gate Byte1"},
122 {0, 2, DDR_PHY_DXNRDQSGDLY(0, 2), 0, "Gate Byte2"},
123 {0, 3, DDR_PHY_DXNRDQSGDLY(0, 3), 0, "Gate Byte3"},
174 {1, 0, DDR_PHY_DXNRDQSGDLY(1, 0), 0, "Gate Byte0"},
175 {1, 1, DDR_PHY_DXNRDQSGDLY(1, 1), 0, "Gate Byte1"},
176 {1, 2, DDR_PHY_DXNRDQSGDLY(1, 2), 0, "Gate Byte2"},
177 {1, 3, DDR_PHY_DXNRDQSGDLY(1, 3), 0, "Gate Byte3"},
Dddr_phy_s40.h73 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t16.h82 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t28.h82 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_s28_v300.h85 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t12_v101.h68 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) macro
Dddr_phy_t12_v100.h68 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) macro
Dddr_training_impl.c2843 base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); in ddr_gate_find_phase()
2858 base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); in ddr_gate_find_phase()
2908 base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, j)); in ddr_gate_find_bdl()
2943 def_delay[i] = ddr_read(base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); in ddr_gate_training()
2956 tmp = ddr_read(base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); in ddr_gate_training()
2959 ddr_write(tmp, base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); in ddr_gate_training()
2965 base_phy + DDR_PHY_DXNRDQSGDLY(cfg->rank_idx, i)); in ddr_gate_training()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/cmd_bin/
Dddr_training_cmd.c333 base_phy + DDR_PHY_DXNRDQSGDLY(rank, i), in dump_result()
334 ddr_read(base_phy + DDR_PHY_DXNRDQSGDLY(rank, i)), i); in dump_result()