Home
last modified time | relevance | path

Searched refs:DDR_PHY_SWTRLT (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h33 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ macro
Dddr_phy_t16.h38 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ macro
Dddr_phy_t28.h36 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ macro
Dddr_phy_s28_v300.h39 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result */ macro
Dddr_phy_t12_v101.h39 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ macro
Dddr_phy_t12_v100.h39 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ macro
Dddr_training_impl.c2685 wl_result = ddr_read(base_phy + DDR_PHY_SWTRLT) in ddr_wl_process()
2887 gate_result = (ddr_read(base_phy + DDR_PHY_SWTRLT) >> 8) in ddr_gate_find_bdl()