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Searched refs:NUM_3 (Results 1 – 25 of 43) sorted by relevance

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/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/
Dlowlevel_init_v300.c190 ddrc_isvalid[NUM_3] = in ddr_scramb()
203 if (ddrc_isvalid[NUM_3]) in ddr_scramb()
214 reg_val[NUM_3] = ddrc_isvalid[NUM_3] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
216 } while (!(reg_val[NUM_0] & reg_val[NUM_1] & reg_val[NUM_2] & reg_val[NUM_3])); in ddr_scramb()
243 if (ddrc_isvalid[NUM_3]) in ddr_scramb()
254 reg_val[NUM_3] = ddrc_isvalid[NUM_3] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
256 } while (reg_val[NUM_0] | reg_val[NUM_1] | reg_val[NUM_2] | reg_val[NUM_3]); in ddr_scramb()
369 cpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
377 mda_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
385 gpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/
Dlowlevel_init_v300.c190 ddrc_isvalid[NUM_3] = in ddr_scramb()
203 if (ddrc_isvalid[NUM_3]) in ddr_scramb()
214 reg_val[NUM_3] = ddrc_isvalid[NUM_3] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
216 } while (!(reg_val[NUM_0] & reg_val[NUM_1] & reg_val[NUM_2] & reg_val[NUM_3])); in ddr_scramb()
243 if (ddrc_isvalid[NUM_3]) in ddr_scramb()
254 reg_val[NUM_3] = ddrc_isvalid[NUM_3] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
256 } while (reg_val[NUM_0] | reg_val[NUM_1] | reg_val[NUM_2] | reg_val[NUM_3]); in ddr_scramb()
369 cpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
377 mda_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
385 gpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/
Dlowlevel_init_v300.c318 core_value[NUM_3] = 0; in get_hpm_value()
323 mda_value[NUM_3] = 0; in get_hpm_value()
328 cpu_value[NUM_3] = 0; in get_hpm_value()
338 cpu_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
346 mda_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
354 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/
Dpll_trainning.c446 regulator->steps[NUM_3] = regulator->curr - step_25; in svb_voltage_regulator_init()
448 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
471 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
474 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
475 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c164 core_value[NUM_3] = 0; in get_hpm_value()
171 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/
Dpll_trainning.c438 regulator->steps[NUM_3] = regulator->curr - step_25; in svb_voltage_regulator_init()
440 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
463 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
466 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
467 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c162 core_value[NUM_3] = 0; in get_hpm_value()
171 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/
Dpll_trainning.c465 regulator->steps[NUM_3] = regulator->curr - step_30; in svb_voltage_regulator_init()
467 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
490 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
493 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
494 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c158 core_value[NUM_3] = 0; in get_hpm_value()
167 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/
Dpll_trainning.c503 regulator->steps[NUM_3] = regulator->curr - step_30; in svb_voltage_regulator_init()
505 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
512 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
515 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
516 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c276 core_value[NUM_3] = 0; in get_hpm_value()
286 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/
Dpll_trainning.c465 regulator->steps[NUM_3] = regulator->curr - step_30; in svb_voltage_regulator_init()
467 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
490 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
493 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
494 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c161 core_value[NUM_3] = 0; in get_hpm_value()
170 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/
Dpll_trainning.c502 regulator->steps[NUM_3] = regulator->curr - step_30; in svb_voltage_regulator_init()
504 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
511 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
514 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
515 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c274 core_value[NUM_3] = 0; in get_hpm_value()
284 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/
Dpll_trainning.c502 regulator->steps[NUM_3] = regulator->curr - step_30; in svb_voltage_regulator_init()
504 regulator->steps[NUM_3] = regulator->min; in svb_voltage_regulator_init()
511 if (regulator->steps[NUM_3] <= regulator->steps[NUM_4]) in svb_voltage_regulator_init()
514 if (regulator->steps[NUM_2] <= regulator->steps[NUM_3]) in svb_voltage_regulator_init()
515 regulator->steps[NUM_3] = 0xffffffff; in svb_voltage_regulator_init()
Dlowlevel_init_v300.c274 core_value[NUM_3] = 0; in get_hpm_value()
284 core_value[NUM_3] += (temp >> 16) & 0x3ff; /* get hight 16 bits */ in get_hpm_value()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/
Dhisvb.c124 cpu_value[NUM_3] += (temp >> 16) & mask; /* get hight 16 bits */ in get_hpm_value()
132 mda_value[NUM_3] += (temp >> 16) & mask; /* get hight 16 bits */ in get_hpm_value()
140 core_value[NUM_3] += (temp >> 16) & mask; /* get hight 16 bits */ in get_hpm_value()
Dhisvb.h40 #define NUM_3 3 macro
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3516dv300/
Dplatform.h217 #define NUM_3 3 macro
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3516cv500/
Dplatform.h217 #define NUM_3 3 macro
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3516av300/
Dplatform.h217 #define NUM_3 3 macro
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3516dv200/
Dplatform.h246 #define NUM_3 3 macro
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3518ev300/
Dplatform.h246 #define NUM_3 3 macro
/third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3516ev300/
Dplatform.h246 #define NUM_3 3 macro

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