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Searched refs:PHY_ACADDRBDL_ADDR1_BIT (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h124 #define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ macro
Dddr_phy_t16.h154 #define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ macro
Dddr_phy_t28.h154 #define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ macro
Dddr_phy_s28_v300.h169 #define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ macro
Dddr_phy_t12_v101.h138 #define PHY_ACADDRBDL_ADDR1_BIT 17 /* [17] ADDR1 delay line */ macro
Dddr_phy_t12_v100.h139 #define PHY_ACADDRBDL_ADDR1_BIT 17 /* [17] ADDR1 delay line */ macro
Dddr_training_impl.c3405 ddr_write(bdl | (bdl << PHY_ACADDRBDL_ADDR1_BIT), in ddr_lpca_set_bdl()
3421 ddr_write(addr0 | (addr1 << PHY_ACADDRBDL_ADDR1_BIT), in ddr_lpca_update_bdl()