Home
last modified time | relevance | path

Searched refs:PHY_ACPHY_DCLK0_BIT (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h128 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ macro
Dddr_phy_t16.h148 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ macro
Dddr_phy_t28.h148 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ macro
Dddr_phy_s28_v300.h163 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ macro
Dddr_phy_t12_v101.h132 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ macro
Dddr_phy_t12_v100.h133 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ macro
Dddr_training_impl.c3025 | ((ac_phy_ctl >> PHY_ACPHY_DCLK0_BIT) in ddr_ac_get_clk()
3041 ac_phy_ctl &= (~(PHY_ACPHY_DCLK_MASK << PHY_ACPHY_DCLK0_BIT)); in ddr_ac_set_clk()
3049 ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK0_BIT); /* set cp1p_dclk0 */ in ddr_ac_set_clk()