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Searched refs:PHY_ACPHY_DCLK1_BIT (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h129 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ macro
Dddr_phy_t16.h149 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ macro
Dddr_phy_t28.h149 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ macro
Dddr_phy_s28_v300.h164 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ macro
Dddr_phy_t12_v101.h133 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ macro
Dddr_phy_t12_v100.h134 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ macro
Dddr_training_impl.c3043 ac_phy_ctl &= (~(PHY_ACPHY_DCLK_MASK << PHY_ACPHY_DCLK1_BIT)); in ddr_ac_set_clk()
3050 ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK1_BIT); /* set cp2p_dclk1 */ in ddr_ac_set_clk()