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Searched refs:PHY_BDL_MASK (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_training_impl.c552 val |= ((PHY_BDL_MASK & value) << ((dq << 3) + PHY_BDL_DQ_BIT)); in ddr_phy_set_dq_bdl()
581 val = (ddr_read(cfg->cur_phy + offset) >> ((dq << 3) + PHY_BDL_DQ_BIT)) & PHY_BDL_MASK; in ddr_phy_get_dq_bdl()
640 dq_val = (dq_val > PHY_BDL_MASK ? PHY_BDL_MASK : dq_val); in ddr_rdqs_sync_rank_rdq()
668 bdl[0] = (dq03 >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
669 bdl[1] = (dq03 >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
670 bdl[2] = (dq03 >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
671 bdl[3] = (dq03 >> PHY_BDL_DQ3_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
672 bdl[4] = (dq47 >> PHY_BDL_DQ0_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
673 bdl[5] = (dq47 >> PHY_BDL_DQ1_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
674 bdl[6] = (dq47 >> PHY_BDL_DQ2_BIT) & PHY_BDL_MASK; in ddr_bdl_adj()
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Dddr_phy_s40.h85 #define PHY_BDL_MASK 0x1f /* [4:0] */ macro
Dddr_phy_t16.h101 #define PHY_BDL_MASK 0x7f /* [6:0] */ macro
Dddr_phy_t28.h101 #define PHY_BDL_MASK 0x7f /* [6:0] */ macro
Dddr_phy_s28_v300.h111 #define PHY_BDL_MASK 0x7f /* [6:0] */ macro
Dddr_phy_t12_v101.h82 #define PHY_BDL_MASK 0x7f /* [7:1] */ macro
Dddr_phy_t12_v100.h82 #define PHY_BDL_MASK 0x7f /* [7:1] */ macro