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Searched refs:PHY_DQ_BDL_MIDDLE (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h229 #define PHY_DQ_BDL_MIDDLE 15 /* middle DQ BDL value */ macro
Dddr_phy_t16.h255 #define PHY_DQ_BDL_MIDDLE 48 /* special middle DQ BDL value */ macro
Dddr_phy_t28.h251 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ macro
Dddr_phy_s28_v300.h269 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ macro
Dddr_phy_t12_v101.h267 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ macro
Dddr_phy_t12_v100.h268 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ macro
Dddr_training_impl.c951 if (dq_bdl > PHY_DQ_BDL_MIDDLE) in ddr_adjust_trend_check()
952 *accel = dq_bdl - PHY_DQ_BDL_MIDDLE; in ddr_adjust_trend_check()
953 else if (dq_bdl < PHY_DQ_BDL_MIDDLE) in ddr_adjust_trend_check()
954 *accel = PHY_DQ_BDL_MIDDLE - dq_bdl; in ddr_adjust_trend_check()
957 cfg->cur_byte, dq_bdl, PHY_DQ_BDL_MIDDLE, *accel, in ddr_adjust_trend_check()
963 if (dq_bdl < (PHY_DQ_BDL_MIDDLE - size)) in ddr_adjust_trend_check()
966 else if (dq_bdl > (PHY_DQ_BDL_MIDDLE + size)) in ddr_adjust_trend_check()