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Searched refs:PHY_DQ_MIDDLE_VAL (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h207 #define PHY_DQ_MIDDLE_VAL 0x10101010 macro
Dddr_phy_t16.h232 #define PHY_DQ_MIDDLE_VAL 0x30303030 macro
Dddr_phy_t28.h229 #define PHY_DQ_MIDDLE_VAL 0x30303030 macro
Dddr_phy_s28_v300.h247 #define PHY_DQ_MIDDLE_VAL 0x30303030 macro
Dddr_phy_t12_v101.h226 #define PHY_DQ_MIDDLE_VAL 0x30303030 macro
Dddr_phy_t12_v100.h227 #define PHY_DQ_MIDDLE_VAL 0x30303030 macro
Dddr_training_impl.c1492 + (PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT), in ddr_hw_read_adj()
1495 + (PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT), in ddr_hw_read_adj()
1967 …ddr_write(PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT, base_phy + DDR_PHY_DXNRDQNBDL0(cfg->rank_idx, byte_… in ddr_mpr_find_rdqs()
1968 …ddr_write(PHY_DQ_MIDDLE_VAL << PHY_BDL_DQ_BIT, base_phy + DDR_PHY_DXNRDQNBDL1(cfg->rank_idx, byte_… in ddr_mpr_find_rdqs()