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Searched refs:PHY_GATE_BDL_MAX (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h210 #define PHY_GATE_BDL_MAX 0x40 /* [4:0]rdqsg_bdl + [20:16]rdqsgtxbdl */ macro
Dddr_phy_t16.h234 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ macro
Dddr_phy_t28.h231 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ macro
Dddr_phy_s28_v300.h249 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ macro
Dddr_phy_t12_v101.h228 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ macro
Dddr_phy_t12_v100.h229 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ macro
Dddr_training_impl.c2884 for (i = 0; i < PHY_GATE_BDL_MAX; i++) { in ddr_gate_find_bdl()
2917 if (i == PHY_GATE_BDL_MAX) { /* find gate bdl fail */ in ddr_gate_find_bdl()