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Searched refs:PHY_RDQSG_PHASE_BIT (Results 1 – 7 of 7) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h113 #define PHY_RDQSG_PHASE_BIT 8 /* [CUSTOM] */ macro
Dddr_phy_t16.h134 #define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ macro
Dddr_phy_t28.h134 #define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ macro
Dddr_phy_s28_v300.h149 #define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ macro
Dddr_phy_t12_v101.h118 #define PHY_RDQSG_PHASE_BIT 10 /* [CUSTOM] */ macro
Dddr_phy_t12_v100.h119 #define PHY_RDQSG_PHASE_BIT 10 /* [CUSTOM] */ macro
Dddr_training_impl.c2842 ddr_write(rdqsg->phase[i] << PHY_RDQSG_PHASE_BIT, in ddr_gate_find_phase()
2857 ddr_write(rdqsg->phase[i] << PHY_RDQSG_PHASE_BIT, in ddr_gate_find_phase()
2900 << PHY_RDQSG_PHASE_BIT) in ddr_gate_find_bdl()
2904 << PHY_RDQSG_PHASE_BIT) in ddr_gate_find_bdl()
2957 tmp &= ~(PHY_RDQSG_PHASE_MASK << PHY_RDQSG_PHASE_BIT); in ddr_gate_training()
2958 tmp |= rdqsg.phase[i] << PHY_RDQSG_PHASE_BIT; in ddr_gate_training()