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Searched refs:PHY_WDQ_PHASE_BIT (Results 1 – 8 of 8) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_s40.h117 #define PHY_WDQ_PHASE_BIT 8 macro
Dddr_training_impl.c994 >> PHY_WDQ_PHASE_BIT) & PHY_WDQ_PHASE_MASK; in ddr_adjust_get_val()
1044 delay = delay & (~(PHY_WDQ_PHASE_MASK << PHY_WDQ_PHASE_BIT)); in ddr_adjust_set_val()
1046 ddr_write(delay | ((unsigned int)val << PHY_WDQ_PHASE_BIT), in ddr_adjust_set_val()
2540 >> PHY_WDQ_PHASE_BIT) in ddr_wl_wdq_adjust()
2580 ddr_write(wdq_phase << PHY_WDQ_PHASE_BIT, in ddr_wl_wdq_adjust()
2616 >> PHY_WDQ_PHASE_BIT) in ddr_wl_bdl_sync()
2652 ddr_write(wdq_phase << PHY_WDQ_PHASE_BIT, in ddr_wl_bdl_sync()
3143 - ((def_phase->bdl[i] >> PHY_WDQ_PHASE_BIT) in ddr_ac_check_clk()
3153 + (phase_range << PHY_WDQ_PHASE_BIT), in ddr_ac_check_clk()
3253 - ((wdq_phase >> PHY_WDQ_PHASE_BIT) in ddr_ac_training()
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Dddr_phy_t16.h138 #define PHY_WDQ_PHASE_BIT 8 macro
Dddr_phy_t28.h138 #define PHY_WDQ_PHASE_BIT 8 macro
Dddr_phy_s28_v300.h153 #define PHY_WDQ_PHASE_BIT 8 macro
Dddr_phy_t12_v101.h122 #define PHY_WDQ_PHASE_BIT 9 macro
Dddr_phy_t12_v100.h123 #define PHY_WDQ_PHASE_BIT 9 macro
Dddr_cmd_ctl.c208 >> PHY_WDQ_PHASE_BIT) & PHY_WDQ_PHASE_MASK; in ddr_cmd_result_print_dataeye()