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Searched refs:SYSCTRL_DDR_HW_PHY1_RANK1 (Results 1 – 15 of 15) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3519av100/
Dddr_training_custom.h91 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3556av100/
Dddr_training_custom.h92 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv300/
Dddr_training_custom.h90 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516av300/
Dddr_training_custom.h90 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3559av100/
Dddr_training_custom.h86 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c macro
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516cv500/
Dddr_training_custom.h90 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev200/
Dddr_training_custom.h91 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev300/
Dddr_training_custom.h91 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3518ev300/
Dddr_training_custom.h91 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv200/
Dddr_training_custom.h91 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3520dv500/
Dddr_training_custom.h80 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c macro
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3521dv200/
Dddr_training_custom.h80 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c macro
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3535av100/
Dddr_training_custom.h82 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c macro
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3531dv200/
Dddr_training_custom.h82 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c macro
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_training_impl.c181 cfg->phy[1].rank[1].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK1); in ddr_training_cfg_set_rank()
184 if (ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK1)) { in ddr_training_cfg_set_rank()
191 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK1), cfg->phy[1].rank[1].item_hw); in ddr_training_cfg_set_rank()