Home
last modified time | relevance | path

Searched refs:base_phy (Results 1 – 12 of 12) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_phy_t12_v101.h309 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
313 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
315 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
316 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
318 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
320 …ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte…
321 …ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte…
325 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
328 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
331 …val = (ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) >> PHY_VRFTRES_RXDIFFCAL_BIT) \
[all …]
Dddr_phy_t12_v100.h310 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
314 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
316 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
317 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
319 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
321 …ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte…
322 …ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte…
326 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
329 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
332 …val = (ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) >> PHY_VRFTRES_RXDIFFCAL_BIT) \
[all …]
Dddr_phy_s28_v300.h326 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
329 hvreft = ddr_read((base_phy) + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
331 ddr_write(hvreft | (val), (base_phy) + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
332 ddr_write(hvreft | (val), (base_phy) + DDR_PHY_HVREFT_STATUS(rank, (byte_index) + 1)); \
335 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
337 val = ddr_read((base_phy) + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
353 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
358 (base_phy) + DDR_PHY_HVREFT_STATUS(rank, _i), \
359 ddr_read((base_phy) \
365 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
[all …]
Dddr_phy_t28.h292 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
295 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
297 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
298 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
301 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
303 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
319 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
324 base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \
325 ddr_read(base_phy \
331 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
[all …]
Dddr_phy_t16.h296 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
301 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(i)) \
304 base_phy + DDR_PHY_HVREFT_STATUS(i)); \
308 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
310 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(0)) \
322 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
326 base_phy + DDR_PHY_HVREFT_STATUS(i), \
327 ddr_read(base_phy \
333 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
336 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \
[all …]
Dddr_training_impl.c305 unsigned int base_phy = cfg->cur_phy; in ddr_training_save_reg() local
312 relate_reg->misc_scramb = ddr_read(base_phy + DDR_PHY_MISC); in ddr_training_save_reg()
315 ddr_read(base_phy + DDR_PHY_ACPHYCTL4); in ddr_training_save_reg()
317 ddr_read(base_phy + DDR_PHY_ACPHYCTL4); in ddr_training_save_reg()
332 if (!(ddr_read(base_phy + DDR_PHY_DRAMCFG) & PHY_DRAMCFG_MA2T)) /* set 1T */ in ddr_training_save_reg()
333 ddr_write(0x0, base_phy + DDR_PHY_ACPHYCTL4); in ddr_training_save_reg()
336 if (!(ddr_read(base_phy + DDR_PHY_DRAMCFG) & PHY_DRAMCFG_MA2T)) /* set 1T */ in ddr_training_save_reg()
337 ddr_write(0x0, base_phy + DDR_PHY_ACPHYCTL4); in ddr_training_save_reg()
346 base_phy + DDR_PHY_MISC); in ddr_training_save_reg()
348 DDR_DQSSWAP_SAVE_FUNC(relate_reg->swapdfibyte_en, base_phy); in ddr_training_save_reg()
[all …]
Dddr_phy_s40.h268 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
270 base_phy + DDR_PHY_IOCTL2)
272 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
276 val = ddr_read(base_phy + DDR_PHY_IOCTL2); \
287 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
289 base_phy + DDR_PHY_IOCTL2, \
290 ddr_read(base_phy + DDR_PHY_IOCTL2));
293 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) argument
294 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) argument
296 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) argument
[all …]
Dddr_training_ctl.c37 unsigned int base_phy = DDR_REG_BASE_PHY0; in ddr_sw_training_func() local
40 unsigned int misc_scramb = ddr_read(base_phy + DDR_PHY_MISC); in ddr_sw_training_func()
41 unsigned int dramcfg_ma2t = ddr_read(base_phy + DDR_PHY_DRAMCFG) in ddr_sw_training_func()
46 acphyctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL4); in ddr_sw_training_func()
47 acphyctl = ddr_read(base_phy + DDR_PHY_ACPHYCTL4); in ddr_sw_training_func()
66 base_phy + DDR_PHY_MISC); in ddr_sw_training_func()
69 DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy); in ddr_sw_training_func()
72 if (ddr_read(base_phy + DDR_PHY_PHYINITSTATUS) in ddr_sw_training_func()
74 DDR_FATAL("PHY[%x] hw gating fail.", base_phy); in ddr_sw_training_func()
76 base_phy, -1, -1); in ddr_sw_training_func()
[all …]
Dddr_cmd_ctl.c207 dqs = (ddr_read(ddrtr_data->base_phy + DDR_PHY_DXNWDQDLY(ddrtr_data->rank_idx, j)) in ddr_cmd_result_print_dataeye()
251 dqs = ddr_read(ddrtr_data->base_phy + DDR_PHY_DXNRDQSDLY(j)) in ddr_cmd_result_print_dataeye()
403 unsigned int base_phy = ddrtr_result->phy_st[phy_index].rank_st[rank_index].ddrtr_data.base_phy; in ddr_reg_result_display_by_rank() local
432 ddr_reg->val = ddr_read(base_phy + ddr_reg->offset); in ddr_reg_result_display_by_rank()
434 printf("[0x%08x = 0x%08x] %-32s", base_phy + ddr_reg->offset, in ddr_reg_result_display_by_rank()
463 …DDR_PHY_SWITCH_RANK((unsigned int)ddrtr_result->phy_st[phy_index].rank_st[i].ddrtr_data.base_phy, … in ddr_reg_result_display_by_phy()
Dddr_training_impl.h268 unsigned int base_phy; member
419 void ddr_phy_cfg_update(unsigned int base_phy);
445 unsigned int *base_phy);
Dddr_interface.h98 unsigned int base_phy; member
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/cmd_bin/
Dddr_training_cmd.c161 ddrtr_res->phy_st[i].rank_st[j].ddrtr_data.base_phy = cfg->phy[i].addr; in ddr_training_result_init()
208 if (result_st->ddrtr_data[index].base_phy == data->base_phy) in ddr_lpca_data_save()
245 unsigned int base_phy = ddrtr_data->base_phy; in dump_result() local
251 ACPHYCTL7 = ddr_read(base_phy + DDR_PHY_ACPHYCTL7); in dump_result()
252 ACPHYCTL7 = ddr_read(base_phy + DDR_PHY_ACPHYCTL7); in dump_result()
268 base_phy + DDR_PHY_DXWDQSDLY(rank, i), in dump_result()
269 ddr_read(base_phy + DDR_PHY_DXWDQSDLY(rank, i)), i); in dump_result()
275 base_phy + DDR_PHY_DXNWDQDLY(rank, i), in dump_result()
276 ddr_read(base_phy + DDR_PHY_DXNWDQDLY(rank, i)), i); in dump_result()
283 base_phy + DDR_PHY_DXNWDQNBDL0(rank, i), in dump_result()
[all …]