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Searched refs:ddr (Results 1 – 25 of 244) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/ddr/fsl/
Dmpc85xx_ddr_gen3.c28 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
58 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
95 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
98 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
Dfsl_ddr_gen4.c55 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
76 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
80 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
85 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
90 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
103 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
106 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
108 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
113 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
115 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
[all …]
Darm_ddr_gen3.c34 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
41 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
45 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
50 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
55 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
67 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
71 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
Dctrl_regs.c148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
295 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_0() argument
438 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
448 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
454 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_3() argument
[all …]
Dmpc86xx_ddr.c18 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
22 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
25 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
Dmpc85xx_ddr_gen2.c19 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
66 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
[all …]
Dmpc85xx_ddr_gen1.c18 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
29 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
45 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
[all …]
/third_party/uboot/u-boot-2020.01/board/sbc8641d/
Dsbc8641d.c100 volatile struct ccsr_ddr *ddr = &immap->im_ddr1; in fixed_sdram() local
102 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
103 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; in fixed_sdram()
104 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
105 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; in fixed_sdram()
106 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
107 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; in fixed_sdram()
108 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
109 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; in fixed_sdram()
110 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/arch/powerpc/cpu/mpc83xx/
Decc.c19 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status() local
21 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status() local
25 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); in ecc_print_status()
30 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); in ecc_print_status()
32 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); in ecc_print_status()
34 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); in ecc_print_status()
39 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); in ecc_print_status()
41 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); in ecc_print_status()
43 (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); in ecc_print_status()
47 ddr->data_err_inject_hi, ddr->data_err_inject_lo); in ecc_print_status()
[all …]
Dspd_sdram.c30 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
33 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
37 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
39 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
44 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) in board_add_ram_info()
50 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) in board_add_ram_info()
129 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
160 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); in spd_sdram()
223 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
224 ddr->cs_config[0] = ( 1 << 31 in spd_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/bsc9132qds/
Dspl_minimal.c19 struct ccsr_ddr __iomem *ddr = in sdram_init() local
22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
[all …]
/third_party/uboot/u-boot-2020.01/post/cpu/mpc83xx/
Decc.c25 static inline void ecc_clear(ddr83xx_t *ddr) in ecc_clear() argument
28 __raw_writel(0, &ddr->capture_address); in ecc_clear()
29 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
30 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
31 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
32 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
35 out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT); in ecc_clear()
38 out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\ in ecc_clear()
52 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; in ecc_post_test() local
64 if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { in ecc_post_test()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/ls1021atsn/
Dls1021atsn.c26 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; in ddrmc_init() local
29 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
31 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
32 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
34 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
35 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
36 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
37 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
38 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
39 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
[all …]
/third_party/uboot/u-boot-2020.01/board/sbc8548/
Dddr.c91 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
94 out_be32(&ddr->cs0_bnds, 0x0000007f); in fixed_sdram()
95 out_be32(&ddr->cs1_bnds, 0x008000ff); in fixed_sdram()
96 out_be32(&ddr->cs2_bnds, 0x00000000); in fixed_sdram()
97 out_be32(&ddr->cs3_bnds, 0x00000000); in fixed_sdram()
99 out_be32(&ddr->cs0_config, 0x80010101); in fixed_sdram()
100 out_be32(&ddr->cs1_config, 0x80010101); in fixed_sdram()
101 out_be32(&ddr->cs2_config, 0x00000000); in fixed_sdram()
102 out_be32(&ddr->cs3_config, 0x00000000); in fixed_sdram()
104 out_be32(&ddr->timing_cfg_3, 0x00000000); in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/bsc9131rdb/
Dspl_minimal.c22 struct ccsr_ddr __iomem *ddr = in sdram_init() local
25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); in sdram_init()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/ls1021aiot/
Dls1021aiot.c48 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; in ddrmc_init() local
51 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
53 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
54 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
56 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
57 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
58 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
59 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
60 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
61 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/mpc8349emds/
Dmpc8349emds.c98 #warning Currenly any ddr size other than 256 is not supported in fixed_sdram()
101 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
102 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
103 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
106 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
107 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
108 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
109 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/mpc8641hpcn/
Dmpc8641hpcn.c70 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; in fixed_sdram() local
72 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
73 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
74 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
75 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
76 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
77 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
78 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; in fixed_sdram()
79 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; in fixed_sdram()
80 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/socrates/
Dsdram.c26 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
32 ddr->cs0_config = 0; in fixed_sdram()
33 ddr->sdram_cfg = 0; in fixed_sdram()
35 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
36 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
37 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
38 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
39 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
40 ddr->sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
41 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/mpc8315erdb/
Dsdram.c57 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; in fixed_sdram()
58 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
61 im->ddr.cs_config[1] = 0; in fixed_sdram()
63 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
64 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
65 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
66 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
67 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
70 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; in fixed_sdram()
72 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/gdsys/mpc8308/
Dsdram.c43 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
44 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
47 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
49 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
51 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
53 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
55 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
56 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/mpc8308_p1m/
Dsdram.c36 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
37 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
40 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
43 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
46 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
48 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
49 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/mpc8308rdb/
Dsdram.c40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
44 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
52 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
53 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/mpc8349itx/
Dmpc8349itx.c45 im->ddr.csbnds[0].csbnds = in fixed_sdram()
49 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
52 im->ddr.cs_config[1] = 0; in fixed_sdram()
53 im->ddr.cs_config[2] = 0; in fixed_sdram()
54 im->ddr.cs_config[3] = 0; in fixed_sdram()
56 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); in fixed_sdram()
57 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); in fixed_sdram()
62 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
63 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ in fixed_sdram()
64 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; in fixed_sdram()
[all …]
/third_party/uboot/u-boot-2020.01/board/freescale/mpc8313erdb/
Dsdram.c63 im->ddr.csbnds[0].csbnds = in fixed_sdram()
67 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
70 im->ddr.cs_config[1] = 0; in fixed_sdram()
72 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; in fixed_sdram()
73 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
76 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
80 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; in fixed_sdram()
83 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; in fixed_sdram()
[all …]

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