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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
83 - description: common_s0 DSS Shared common 0
107 const: 0
109 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7s.dtsi54 #size-cells = <0>;
61 arm,psci-suspend-param = <0x0010000>;
69 cpu0: cpu@0 {
72 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
98 #phy-cells = <0>;
105 #phy-cells = <0>;
124 #size-cells = <0>;
126 port@0 {
[all …]
Dls1021a.dtsi74 #size-cells = <0>;
79 reg = <0xf00>;
80 clocks = <&clockgen 1 0>;
87 reg = <0xf01>;
88 clocks = <&clockgen 1 0>;
95 reg = <0x0 0x0 0x0 0x0>;
100 #clock-cells = <0>;
123 offset = <0xb0>;
124 mask = <0x02>;
137 reg = <0x0 0x1080000 0x0 0x1000>;
[all …]
Dprima2.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0>;
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
51 ranges = <0x40000000 0x40000000 0x80000000>;
55 reg = <0x80040000 0x1000>;
59 arm,filter-ranges = <0 0x40000000>;
66 reg = <0x80020000 0x1000>;
[all …]
Datlas6.dtsi16 #size-cells = <0>;
18 cpu@0 {
19 reg = <0x0>;
25 timebase-frequency = <0>;
26 bus-frequency = <0>;
27 clock-frequency = <0>;
49 ranges = <0x40000000 0x40000000 0x80000000>;
55 reg = <0x80020000 0x1000>;
62 ranges = <0x88000000 0x88000000 0x40000>;
66 reg = <0x88000000 0x1000>;
[all …]
Dpicoxcell-pc3x2.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
31 pclk: clock@0 {
43 ranges = <0 0x80000000 0x400000>;
47 reg = <0x30000 0x10000>;
54 reg = <0x40000 0x10000>;
61 reg = <0x50000 0x10000>;
69 reg = <0x60000 0x1000>;
76 reg = <0x64000 0x1000>;
82 reg = <0x80000 0x10000>;
[all …]
Dexynos5260.dtsi35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x0>;
47 reg = <0x1>;
54 reg = <0x100>;
61 reg = <0x101>;
68 reg = <0x102>;
75 reg = <0x103>;
88 reg = <0x10010000 0x10000>;
94 reg = <0x10200000 0x10000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp.dtsi43 #size-cells = <0>;
45 A53_0: cpu@0 {
48 reg = <0x0>;
59 reg = <0x1>;
70 reg = <0x2>;
81 reg = <0x3>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 #clock-cells = <0>;
117 #clock-cells = <0>;
[all …]
Dimx8mn.dtsi44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xb00>, <0x7>;
133 opp-supported-hw = <0x300>, <0x7>;
141 opp-supported-hw = <0x100>, <0x3>;
[all …]
Dimx8mm.dtsi44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xe>, <0x7>;
133 opp-supported-hw = <0xc>, <0x7>;
141 opp-supported-hw = <0x8>, <0x3>;
[all …]
Dfsl-ls1012a.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
37 clocks = <&clockgen 1 0>;
53 arm,psci-suspend-param = <0x0>;
62 #clock-cells = <0>;
69 #clock-cells = <0>;
84 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
91 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
92 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
Dimx8mq.dtsi46 #clock-cells = <0>;
53 #clock-cells = <0>;
60 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 #clock-cells = <0>;
95 #size-cells = <0>;
97 A53_0: cpu@0 {
100 reg = <0x0>;
[all …]
Dfsl-ls1028a.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
42 reg = <0x1>;
44 clocks = <&clockgen 1 0>;
65 arm,psci-suspend-param = <0x0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 reg = <0x0 0xf1f0000 0x0 0xffff>;
[all …]
Dfsl-ls1046a.dtsi36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0x0>;
42 clocks = <&clockgen 1 0>;
51 reg = <0x1>;
52 clocks = <&clockgen 1 0>;
61 reg = <0x2>;
62 clocks = <&clockgen 1 0>;
71 reg = <0x3>;
72 clocks = <&clockgen 1 0>;
[all …]
Dfsl-ls1043a.dtsi35 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0>;
47 clocks = <&clockgen 1 0>;
56 reg = <0x1>;
57 clocks = <&clockgen 1 0>;
66 reg = <0x2>;
67 clocks = <&clockgen 1 0>;
76 reg = <0x3>;
77 clocks = <&clockgen 1 0>;
[all …]
Dimx8qxp.dtsi52 #size-cells = <0>;
55 A35_0: cpu@0 {
58 reg = <0x0 0x0>;
69 reg = <0x0 0x1>;
80 reg = <0x0 0x2>;
91 reg = <0x0 0x3>;
124 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
125 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
137 reg = <0 0x92400000 0 0x2000000>;
157 mboxes = <&lsio_mu1 0 0
[all …]
Dfsl-ls1088a.dtsi26 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
41 reg = <0x1>;
42 clocks = <&clockgen 1 0>;
50 reg = <0x2>;
51 clocks = <&clockgen 1 0>;
59 reg = <0x3>;
60 clocks = <&clockgen 1 0>;
[all …]
/kernel/linux/linux-5.10/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
71 …R_CONFIG__NUM_PKRS__SHIFT 0x8
72 …__NUM_PKRS_MASK 0x00000700L
74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.txt29 reg = <0 0x0c360000 0 0x10000>,
30 <0 0x0c370000 0 0x10000>,
31 <0 0x0c380000 0 0x10000>,
32 <0 0x0c390000 0 0x10000>;
89 reg = <0 0x0c360000 0 0x10000>,
90 <0 0x0c370000 0 0x10000>,
91 <0 0x0c380000 0 0x10000>,
92 <0 0x0c390000 0 0x10000>;
122 pinctrl-0 = <&sdmmc1_3v3>;
130 pinctrl-0 = <&hdmi_off>;
/kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic_hdr.h21 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
22 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
23 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
24 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
25 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
26 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
27 NETXEN_HW_H6_CH_HUB_ADR = 0x08
30 /* Hub 0 */
32 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
33 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h50 VG1 = 0,
60 MIXER0 = 0,
66 INTF_LCDC_DTV = 0,
78 FRAME_LINEAR = 0,
84 SCALE_FIR = 0,
90 DMA_P = 0,
95 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
96 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
97 #define MDP4_IRQ_DMA_S_DONE 0x00000004
98 #define MDP4_IRQ_DMA_E_DONE 0x00000008
[all …]

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