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Searched refs:GENX (Results 1 – 25 of 53) sorted by relevance

123

/third_party/mesa3d/src/intel/vulkan/
DgenX_gpu_memcpy.c87 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS)); in genX()
88 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1, in genX()
89 &(struct GENX(VERTEX_BUFFER_STATE)) { in genX()
105 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS)); in genX()
106 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1, in genX()
107 &(struct GENX(VERTEX_ELEMENT_STATE)) { in genX()
119 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in genX()
126 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs); in genX()
130 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs); in genX()
131 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs); in genX()
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Dgfx8_cmd_buffer.c52 struct GENX(SF_CLIP_VIEWPORT) sfv = { in gfx8_cmd_buffer_emit_viewport()
85 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv); in gfx8_cmd_buffer_emit_viewport()
89 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) { in gfx8_cmd_buffer_emit_viewport()
115 struct GENX(CC_VIEWPORT) cc_viewport = { in gfx8_cmd_buffer_emit_depth_viewport()
120 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport); in gfx8_cmd_buffer_emit_depth_viewport()
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) { in gfx8_cmd_buffer_emit_depth_viewport()
147 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
167 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
168 lri.RegisterOffset = GENX(CACHE_MODE_0_num); in genX()
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DgenX_state.c89 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4; in genX()
95 struct GENX(SLICE_HASH_TABLE) table; in genX()
98 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table); in genX()
101 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { in genX()
106 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { in genX()
130 anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) { in genX()
148 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) { in genX()
165 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) { in init_render_queue_state()
174 anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) { in init_render_queue_state()
184 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa); in init_render_queue_state()
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Dgfx7_cmd_buffer.c245 uint32_t sf_dw[GENX(3DSTATE_SF_length)]; in genX()
246 struct GENX(3DSTATE_SF) sf = { in genX()
247 GENX(3DSTATE_SF_header), in genX()
260 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); in genX()
269 GENX(COLOR_CALC_STATE_length) * 4, in genX()
271 struct GENX(COLOR_CALC_STATE) cc = { in genX()
279 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc); in genX()
281 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { in genX()
287 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) { in genX()
304 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)]; in genX()
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DgenX_pipeline.c117 GENX(3DSTATE_VERTEX_ELEMENTS)); in emit_vertex_input()
139 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
146 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element); in emit_vertex_input()
167 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
178 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element); in emit_vertex_input()
185 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
209 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
223 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element); in emit_vertex_input()
226 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
233 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_SGVS), sgvs) { in emit_vertex_input()
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DgenX_query.c219 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe); in genX()
611 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_ps_depth_count()
638 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_query_pc_availability()
800 GENX(IA_VERTICES_COUNT_num),
801 GENX(IA_PRIMITIVES_COUNT_num),
802 GENX(VS_INVOCATION_COUNT_num),
803 GENX(GS_INVOCATION_COUNT_num),
804 GENX(GS_PRIMITIVES_COUNT_num),
805 GENX(CL_INVOCATION_COUNT_num),
806 GENX(CL_PRIMITIVES_COUNT_num),
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DgenX_cmd_buffer.c55 convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) { in convert_pc_to_bits()
107 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
139 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { in genX()
272 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
783 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in set_image_compressed_bit()
798 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in set_image_fast_clear_state()
889 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) { in anv_cmd_compute_resolve_predicate()
932 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) { in anv_cmd_simple_resolve_predicate()
1046 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in init_fast_clear_color()
1053 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in init_fast_clear_color()
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/third_party/mesa3d/src/intel/genxml/
Dgen_macros.h63 # define GENX(X) GFX4_##X macro
66 # define GENX(X) GFX45_##X macro
69 # define GENX(X) GFX5_##X macro
72 # define GENX(X) GFX6_##X macro
75 # define GENX(X) GFX7_##X macro
78 # define GENX(X) GFX75_##X macro
81 # define GENX(X) GFX8_##X macro
84 # define GENX(X) GFX9_##X macro
87 # define GENX(X) GFX11_##X macro
90 # define GENX(X) GFX12_##X macro
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/third_party/mesa3d/src/intel/blorp/
Dblorp_genX_exec.h246 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in emit_urb_config()
254 blorp_emit(batch, GENX(3DSTATE_URB_VS), urb) { in emit_urb_config()
362 blorp_fill_vertex_buffer_state(struct GENX(VERTEX_BUFFER_STATE) *vb, in blorp_fill_vertex_buffer_state()
399 struct GENX(VERTEX_BUFFER_STATE) vb[3]; in blorp_emit_vertex_buffers()
414 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers()
415 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords); in blorp_emit_vertex_buffers()
420 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]); in blorp_emit_vertex_buffers()
421 dw += GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers()
434 struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements]; in blorp_emit_vertex_elements()
485 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { in blorp_emit_vertex_elements()
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/third_party/mesa3d/src/intel/isl/
Disl_emit_depth_stencil.c72 struct GENX(3DSTATE_DEPTH_BUFFER) db = { in isl_genX()
73 GENX(3DSTATE_DEPTH_BUFFER_header), in isl_genX()
161 struct GENX(3DSTATE_STENCIL_BUFFER) sb = { in isl_genX()
162 GENX(3DSTATE_STENCIL_BUFFER_header), in isl_genX()
220 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = { in isl_genX()
221 GENX(3DSTATE_HIER_DEPTH_BUFFER_header), in isl_genX()
223 struct GENX(3DSTATE_CLEAR_PARAMS) clear = { in isl_genX()
224 GENX(3DSTATE_CLEAR_PARAMS_header), in isl_genX()
322 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db); in isl_genX()
323 dw += GENX(3DSTATE_DEPTH_BUFFER_length); in isl_genX()
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Disl_surface_state.c290 struct GENX(RENDER_SURFACE_STATE) s = { 0 }; in isl_genX()
576 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; in isl_genX()
577 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; in isl_genX()
578 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; in isl_genX()
579 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; in isl_genX()
852 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); in isl_genX()
894 struct GENX(RENDER_SURFACE_STATE) s = { 0, }; in isl_genX()
979 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; in isl_genX()
980 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g; in isl_genX()
981 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b; in isl_genX()
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/third_party/mesa3d/src/gallium/drivers/iris/
Diris_state.c476 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in _iris_emit_lri()
481 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
486 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) { in _iris_emit_lrr()
530 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_load_register_mem32()
555 iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) { in iris_store_register_mem32()
578 iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) { in iris_store_data_imm32()
595 _iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) { in iris_store_data_imm64()
616 iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) { in iris_copy_mem_mem()
640 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), t); in emit_pipeline_select()
668 iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) { in emit_pipeline_select()
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Diris_query.c51 #define SO_PRIM_STORAGE_NEEDED(n) (GENX(SO_PRIM_STORAGE_NEEDED0_num) + (n) * 8)
52 #define SO_NUM_PRIMS_WRITTEN(n) (GENX(SO_NUM_PRIMS_WRITTEN0_num) + (n) * 8)
212 GENX(CL_INVOCATION_COUNT_num) : in write_value()
223 GENX(IA_VERTICES_COUNT_num), in write_value()
224 GENX(IA_PRIMITIVES_COUNT_num), in write_value()
225 GENX(VS_INVOCATION_COUNT_num), in write_value()
226 GENX(GS_INVOCATION_COUNT_num), in write_value()
227 GENX(GS_PRIMITIVES_COUNT_num), in write_value()
228 GENX(CL_INVOCATION_COUNT_num), in write_value()
229 GENX(CL_PRIMITIVES_COUNT_num), in write_value()
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/third_party/mesa3d/src/panfrost/lib/
Dpan_cs.h148 GENX(pan_emit_tls)(const struct pan_tls_info *info,
152 GENX(pan_select_crc_rt)(const struct pan_fb_info *fb);
159 GENX(pan_select_crc_rt)(fb) >= 0); in pan_fbd_has_zs_crc_ext()
163 GENX(pan_emit_fbd)(const struct panfrost_device *dev,
171 GENX(pan_emit_tiler_heap)(const struct panfrost_device *dev,
175 GENX(pan_emit_tiler_ctx)(const struct panfrost_device *dev,
183 GENX(pan_emit_fragment_job)(const struct pan_fb_info *fb,
Dpan_blitter.h85 GENX(pan_blitter_init)(struct panfrost_device *dev,
90 GENX(pan_blitter_cleanup)(struct panfrost_device *dev);
93 GENX(pan_preload_fb)(struct pan_pool *desc_pool,
100 GENX(pan_blit_ctx_init)(struct panfrost_device *dev,
124 GENX(pan_blit)(struct pan_blit_context *ctx,
Dpan_indirect_dispatch.h40 GENX(pan_indirect_dispatch_emit)(struct pan_pool *pool,
45 GENX(pan_indirect_dispatch_init)(struct panfrost_device *dev);
48 GENX(pan_indirect_dispatch_cleanup)(struct panfrost_device *dev);
Dpan_indirect_draw.h52 GENX(panfrost_emit_indirect_draw)(struct pan_pool *pool,
58 GENX(panfrost_init_indirect_draw_shaders)(struct panfrost_device *dev,
62 GENX(panfrost_cleanup_indirect_draw_shaders)(struct panfrost_device *dev);
Dpan_blend.h161 GENX(pan_blend_create_shader)(const struct panfrost_device *dev,
169 GENX(pan_blend_get_internal_desc)(const struct panfrost_device *dev,
178 GENX(pan_blend_get_shader_locked)(const struct panfrost_device *dev,
/third_party/mesa3d/src/mesa/drivers/dri/i965/
DgenX_state_upload.c82 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) { in emit_lrm()
93 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) { in emit_lri()
112 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) { in genX()
151 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) { in genX()
187 brw_batch_emit(brw, GENX(3DSTATE_LINE_STIPPLE), line) { in genX()
212 brw_batch_emit(brw, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in genX()
237 struct GENX(VERTEX_BUFFER_STATE) buf_state = { in genX()
278 GENX(VERTEX_BUFFER_STATE_pack)(brw, dw, &buf_state); in genX()
279 return dw + GENX(VERTEX_BUFFER_STATE_length); in genX()
493 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs) { in genX()
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Dgfx4_blorp_exec.h55 blorp_emit_dynamic(batch, GENX(VS_STATE), vs, 64, &offset) { in blorp_emit_vs_state()
77 blorp_emit_dynamic(batch, GENX(SF_STATE), sf, 64, &offset) { in blorp_emit_sf_state()
113 blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) { in blorp_emit_wm_state()
167 blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { in blorp_emit_color_calc_state()
183 blorp_emit(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) { in blorp_emit_pipeline()
194 blorp_emit(batch, GENX(CS_URB_STATE), curb); in blorp_emit_pipeline()
195 blorp_emit(batch, GENX(CONSTANT_BUFFER), curb); in blorp_emit_pipeline()
/third_party/mesa3d/src/panfrost/lib/genxml/
Dgen_macros.h82 # define GENX(X) X##_v4 macro
85 # define GENX(X) X##_v5 macro
88 # define GENX(X) X##_v6 macro
91 # define GENX(X) X##_v7 macro
/third_party/mesa3d/src/intel/common/
Dmi_builder.h168 mi_builder_pack(b, GENX(MI_MATH), dw, math) { in mi_builder_flush_math()
169 math.DWordLength = 1 + b->num_math_dwords - GENX(MI_MATH_length_bias); in mi_builder_flush_math()
386 … GENX(MI_LOAD_REGISTER_IMM_length) + 2); in _mi_copy_no_unref()
388 mi_builder_pack(b, GENX(MI_LOAD_REGISTER_IMM), dw, lri) { in _mi_copy_no_unref()
389 lri.DWordLength = GENX(MI_LOAD_REGISTER_IMM_length) + 2 - in _mi_copy_no_unref()
390 GENX(MI_LOAD_REGISTER_IMM_length_bias); in _mi_copy_no_unref()
403 GENX(MI_STORE_DATA_IMM_length) + 1); in _mi_copy_no_unref()
404 mi_builder_pack(b, GENX(MI_STORE_DATA_IMM), dw, sdm) { in _mi_copy_no_unref()
405 sdm.DWordLength = GENX(MI_STORE_DATA_IMM_length) + 1 - in _mi_copy_no_unref()
406 GENX(MI_STORE_DATA_IMM_length_bias); in _mi_copy_no_unref()
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/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_state.c377 crocus_emit_cmd(batch, GENX(MI_FLUSH), foo); in upload_pipelined_state_pointers()
380 crocus_emit_cmd(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) { in upload_pipelined_state_pointers()
494 crocus_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) { in crocus_store_register_mem32()
520 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in _crocus_emit_lri()
525 #define crocus_emit_lri(b, r, v) _crocus_emit_lri(b, GENX(r##_num), v)
531 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) { in _crocus_emit_lrr()
575 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in crocus_load_register_mem32()
599 crocus_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) { in crocus_store_data_imm32()
616 _crocus_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) { in crocus_store_data_imm64()
652 uint32_t sf[GENX(3DSTATE_SF_length)];
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Dgen4_blorp_exec.h53 blorp_emit_dynamic(blorp_batch, GENX(VS_STATE), vs, 64, &offset) { in blorp_emit_vs_state()
74 blorp_emit_dynamic(blorp_batch, GENX(SF_STATE), sf, 64, &offset) { in blorp_emit_sf_state()
108 blorp_emit_dynamic(blorp_batch, GENX(WM_STATE), wm, 64, &offset) { in blorp_emit_wm_state()
162 blorp_emit_dynamic(blorp_batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { in blorp_emit_color_calc_state()
177 blorp_emit(blorp_batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) { in blorp_emit_pipeline()
188 blorp_emit(blorp_batch, GENX(CS_URB_STATE), curb); in blorp_emit_pipeline()
189 blorp_emit(blorp_batch, GENX(CONSTANT_BUFFER), curb); in blorp_emit_pipeline()
Dcrocus_query.c72 #define SO_PRIM_STORAGE_NEEDED(n) (GENX(SO_PRIM_STORAGE_NEEDED0_num) + (n) * 8)
73 #define SO_NUM_PRIMS_WRITTEN(n) (GENX(SO_NUM_PRIMS_WRITTEN0_num) + (n) * 8)
226 GENX(CL_INVOCATION_COUNT_num) : in write_value()
241 GENX(IA_VERTICES_COUNT_num), in write_value()
242 GENX(IA_PRIMITIVES_COUNT_num), in write_value()
243 GENX(VS_INVOCATION_COUNT_num), in write_value()
244 GENX(GS_INVOCATION_COUNT_num), in write_value()
245 GENX(GS_PRIMITIVES_COUNT_num), in write_value()
246 GENX(CL_INVOCATION_COUNT_num), in write_value()
247 GENX(CL_PRIMITIVES_COUNT_num), in write_value()
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