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Searched refs:sih (Results 1 – 25 of 115) sorted by relevance

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/device/board/isoftstone/yangfan/kernel/src/driv/net/rockchip_wlan/rkwifi/bcmdhd/include/
Dsiutils.h242 #define ISSIM_ENAB(sih) TRUE argument
244 #define ISSIM_ENAB(sih) FALSE argument
248 #define ATE_BLD_ENAB(sih) TRUE argument
250 #define ATE_BLD_ENAB(sih) FALSE argument
257 #define PMUCTL_ENAB(sih) (BCMPMUCTL) argument
259 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) argument
263 #define AOB_ENAB(sih) (BCMAOBENAB) argument
265 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \ argument
266 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
271 #define CCCTL_ENAB(sih) (0) argument
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Dhndpmu.h59 #define PMUREGADDR(sih, pmur, ccr, member) \ argument
60 (AOB_ENAB(sih) ? (&(pmur)->member) : (&(ccr)->member))
63 #define HND_PMU_SYNC_WR(sih, pmur, ccr, osh, r, v) do { \ argument
64 if ((sih) && (sih)->pmurev >= 22) { \
65 while (R_REG(osh, PMUREGADDR(sih, pmur, ccr, pmustatus)) & \
186 extern void si_pmu_init(si_t *sih, osl_t *osh);
187 extern void si_pmu_chip_init(si_t *sih, osl_t *osh);
188 extern void si_pmu_pll_init(si_t *sih, osl_t *osh, uint32 xtalfreq);
189 extern void si_pmu_res_init(si_t *sih, osl_t *osh);
190 extern void si_pmu_swreg_init(si_t *sih, osl_t *osh);
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Dhndlhl.h40 extern void si_lhl_timer_config(si_t *sih, osl_t *osh, int timer_type);
41 extern void si_lhl_timer_enable(si_t *sih);
42 extern void si_lhl_timer_reset(si_t *sih, uint coreid, uint coreunit);
44 extern void si_lhl_setup(si_t *sih, osl_t *osh);
45 extern void si_lhl_enable(si_t *sih, osl_t *osh, bool enable);
46 extern void si_lhl_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period);
47 extern void si_lhl_enable_sdio_wakeup(si_t *sih, osl_t *osh);
48 extern void si_lhl_disable_sdio_wakeup(si_t *sih);
49 extern int si_lhl_set_lpoclk(si_t *sih, osl_t *osh, uint32 lpo_force);
50 extern void si_set_lv_sleep_mode_lhl_config_4369(si_t *sih);
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/device/board/isoftstone/zhiyuan/kernel/driver/drivers/net/wireless/bcmdhd/include/
Dsiutils.h157 #define ISSIM_ENAB(sih) FALSE argument
163 #define PMUCTL_ENAB(sih) (BCMPMUCTL) argument
165 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) argument
169 #define AOB_ENAB(sih) (BCMAOBENAB) argument
171 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \ argument
172 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
177 #define CCCTL_ENAB(sih) (0) argument
178 #define CCPLL_ENAB(sih) (0) argument
180 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) argument
181 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) argument
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/device/board/kaihong/khdvk_3566b/wifi/bcmdhd_hdf/bcmdhd/include/
Dsiutils.h164 #define ISSIM_ENAB(sih) FALSE argument
170 #define PMUCTL_ENAB(sih) (BCMPMUCTL) argument
172 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) argument
176 #define AOB_ENAB(sih) (BCMAOBENAB) argument
178 #define AOB_ENAB(sih) \ argument
179 ((sih)->ccrev >= 35 ? ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
184 #define CCCTL_ENAB(sih) (0) argument
185 #define CCPLL_ENAB(sih) (0) argument
187 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) argument
188 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) argument
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Dhndpmu.h38 extern uint32 si_pmu_rsrc_macphy_clk_deps(si_t *sih, osl_t *osh, int maccore_index);
39 extern uint32 si_pmu_rsrc_ht_avail_clk_deps(si_t *sih, osl_t *osh);
41 extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on, uint32* min_res_mask);
42 extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength);
44 extern void si_pmu_slow_clk_reinit(si_t *sih, osl_t *osh);
45 extern void si_pmu_avbtimer_enable(si_t *sih, osl_t *osh, bool set_flag);
46 extern uint32 si_pmu_dump_pmucap_binary(si_t *sih, uchar *p);
47 extern uint32 si_pmu_dump_buf_size_pmucap(si_t *sih);
48 extern int si_pmu_wait_for_steady_state(si_t *sih, osl_t *osh, pmuregs_t *pmu);
49 extern uint32 si_pmu_wake_bit_offset(si_t *sih);
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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
Dsiutils.h163 #define ISSIM_ENAB(sih) FALSE argument
169 #define PMUCTL_ENAB(sih) (BCMPMUCTL) argument
171 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) argument
175 #define AOB_ENAB(sih) (BCMAOBENAB) argument
177 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \ argument
178 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
183 #define CCCTL_ENAB(sih) (0) argument
184 #define CCPLL_ENAB(sih) (0) argument
186 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) argument
187 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) argument
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Dhndpmu.h39 extern uint32 si_pmu_rsrc_macphy_clk_deps(si_t *sih, osl_t *osh, int maccore_index);
40 extern uint32 si_pmu_rsrc_ht_avail_clk_deps(si_t *sih, osl_t *osh);
42 extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on, uint32* min_res_mask);
43 extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength);
45 extern void si_pmu_slow_clk_reinit(si_t *sih, osl_t *osh);
46 extern void si_pmu_avbtimer_enable(si_t *sih, osl_t *osh, bool set_flag);
47 extern uint32 si_pmu_dump_pmucap_binary(si_t *sih, uchar *p);
48 extern uint32 si_pmu_dump_buf_size_pmucap(si_t *sih);
49 extern int si_pmu_wait_for_steady_state(si_t *sih, osl_t *osh, pmuregs_t *pmu);
50 extern uint32 si_pmu_wake_bit_offset(si_t *sih);
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/device/board/isoftstone/yangfan/kernel/src/driv/net/rockchip_wlan/rkwifi/bcmdhd/
Dsiutils.c147 static void si_43012_lp_enable(si_t *sih);
160 static char *si_devpathvar(const si_t *sih, char *var, int len, const char *name);
161 static char *si_pcie_devpathvar(const si_t *sih, char *var, int len, const char *name);
169 static void si_gci_enable_gpioint(si_t *sih, bool enable);
171 static chipcregs_t * seci_set_core(si_t *sih, uint32 *origidx, bool *fast);
177 static void si_oob_war_BT_F1(si_t *sih);
187 static void si_wci2_rxfifo_intr_handler_process(si_t *sih, uint32 intstatus);
444 si_get_pmu_reg_addr(si_t *sih, uint32 offset) in si_get_pmu_reg_addr() argument
446 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr()
465 si_setcoreidx(sih, origidx); in si_get_pmu_reg_addr()
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Dhndpmu.c142 static void si_pmu_chipcontrol_xtal_settings_4369(si_t *sih);
143 static void si_pmu_chipcontrol_xtal_settings_4362(si_t *sih);
144 static void si_pmu_chipcontrol_xtal_settings_4378(si_t *sih);
147 static void si_pmu1_pllinit1(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 xtal);
148 static void si_pmu_pll_off(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *min_mask,
150 static void si_pmu_pll_on(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 min_mask,
152 static void si_pmu_otp_pllcontrol(si_t *sih, osl_t *osh);
153 static void si_pmu_otp_vreg_control(si_t *sih, osl_t *osh);
154 static void si_pmu_otp_chipcontrol(si_t *sih, osl_t *osh);
155 static uint32 si_pmu_def_alp_clock(si_t *sih, osl_t *osh);
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Dhndmem.c39 hndmem_num_banks(si_t *sih, int mem) in hndmem_num_banks() argument
44 osl_t *osh = si_osh(sih); in hndmem_num_banks()
50 savecore = si_coreidx(sih); in hndmem_num_banks()
54 if (!si_setcore(sih, SOCRAM_CORE_ID, 0)) { in hndmem_num_banks()
58 if (GCIREV(sih->gcirev) >= 9) { in hndmem_num_banks()
59 gciregs = si_setcore(sih, GCI_CORE_ID, 0); in hndmem_num_banks()
88 si_setcoreidx(sih, savecore); in hndmem_num_banks()
95 hndmem_bank_size(si_t *sih, hndmem_type_t mem, int bank_num) in hndmem_bank_size() argument
100 osl_t *osh = si_osh(sih); in hndmem_bank_size()
106 savecore = si_coreidx(sih); in hndmem_bank_size()
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Dpcie_core.c69 void pcie_watchdog_reset(osl_t *osh, si_t *sih, uint32 wd_mask, uint32 wd_val) in pcie_watchdog_reset() argument
79 uint32 origidx = si_coreidx(sih); in pcie_watchdog_reset()
86 if (BCM4397_CHIP(sih->chip)) { in pcie_watchdog_reset()
91 if (CCREV(sih->ccrev) < 65) { in pcie_watchdog_reset()
92 si_setcoreidx(sih, origidx); in pcie_watchdog_reset()
97 if (CCREV(sih->ccrev) < 67) { in pcie_watchdog_reset()
99 si_setcoreidx(sih, origidx); in pcie_watchdog_reset()
105 pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0); in pcie_watchdog_reset()
115 if (CCREV(sih->ccrev) >= 65) { in pcie_watchdog_reset()
116 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), wd_mask, wd_val); in pcie_watchdog_reset()
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/device/board/kaihong/khdvk_3566b/wifi/bcmdhd_hdf/bcmdhd/
Dsiutils.c341 uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset) in si_get_pmu_reg_addr() argument
343 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr()
359 si_setcoreidx(sih, origidx); in si_get_pmu_reg_addr()
361 pmuaddr = SI_ENUM_BASE(sih) + offset; in si_get_pmu_reg_addr()
407 struct si_pub *sih = &sii->pub; in si_buscore_setup() local
420 si_corereg(sih, GCI_CORE_IDX(sih), in si_buscore_setup()
421 GCI_OFFSETOF(sih, gci_corecaps0), 0, 0) & in si_buscore_setup()
552 uint16 si_chipid(si_t *sih) in si_chipid() argument
554 si_info_t *sii = SI_INFO(sih); in si_chipid()
556 return (sii->chipnew) ? sii->chipnew : sih->chip; in si_chipid()
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Dhndlhl.c54 void si_lhl_setup(si_t *sih, osl_t *osh) in si_lhl_setup() argument
56 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_lhl_setup()
58 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_2); in si_lhl_setup()
62 LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL); in si_lhl_setup()
63 LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, in si_lhl_setup()
65 LHL_REG(sih, lhl_top_pwrdn_ctl_adr, LHL_PWRDN_CTL_MASK, in si_lhl_setup()
67 LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, in si_lhl_setup()
69 } else if (BCM4347_CHIP(sih->chip)) { in si_lhl_setup()
70 if (LHL_IS_PSMODE_1(sih)) { in si_lhl_setup()
71 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, in si_lhl_setup()
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Dhndpmu.c104 void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength) in si_sdiod_drive_strength_init() argument
116 UNUSED_PARAMETER(sih); in si_sdiod_drive_strength_init()
121 void si_switch_pmu_dependency(si_t *sih, uint mode) in si_switch_pmu_dependency() argument
124 osl_t *osh = si_osh(sih); in si_switch_pmu_dependency()
134 origidx = si_coreidx(sih); in si_switch_pmu_dependency()
135 if (AOB_ENAB(sih)) { in si_switch_pmu_dependency()
136 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_switch_pmu_dependency()
137 cc = si_setcore(sih, CC_CORE_ID, 0); in si_switch_pmu_dependency()
139 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_switch_pmu_dependency()
140 cc = si_setcoreidx(sih, SI_CC_IDX); in si_switch_pmu_dependency()
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Dhndmem.c45 int hndmem_num_banks(si_t *sih, int mem) in hndmem_num_banks() argument
50 osl_t *osh = si_osh(sih); in hndmem_num_banks()
56 savecore = si_coreidx(sih); in hndmem_num_banks()
60 if (!si_setcore(sih, SOCRAM_CORE_ID, 0)) { in hndmem_num_banks()
64 if (sih->gcirev >= 0x9) { in hndmem_num_banks()
65 gciregs = si_setcore(sih, GCI_CORE_ID, 0); in hndmem_num_banks()
95 si_setcoreidx(sih, savecore); in hndmem_num_banks()
101 int hndmem_bank_size(si_t *sih, hndmem_type_t mem, int bank_num) in hndmem_bank_size() argument
106 osl_t *osh = si_osh(sih); in hndmem_bank_size()
112 savecore = si_coreidx(sih); in hndmem_bank_size()
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Dsiutils_priv.h182 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) argument
257 extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
258 extern uint sb_coreid(si_t *sih);
259 extern uint sb_intflag(si_t *sih);
260 extern uint sb_flag(si_t *sih);
261 extern void sb_setint(si_t *sih, int siflag);
262 extern uint sb_corevendor(si_t *sih);
263 extern uint sb_corerev(si_t *sih);
264 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
266 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
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Dotpdefs.h47 #define SROM_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset)) argument
71 #define OTP_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset)) argument
76 #define PCIE_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0x3000) argument
77 #define SPROM_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_CTRL) argument
80 #define SPROM_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_ADDRESS) argument
81 #define SPROM_DATA(sih) (SI_ENUM_BASE(sih) + CC_SROM_DATA) argument
82 #define OTP_CTRL1_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0xF4) argument
83 #define PMU_MINRESMASK_REG_ADDR(sih) (SI_ENUM_BASE(sih) + MINRESMASKREG) argument
84 #define CHIP_COMMON_STATUS_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CHIPST) argument
85 #define CHIP_COMMON_CLKDIV2_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CLKDIV2) argument
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
Dsiutils.c329 si_get_pmu_reg_addr(si_t *sih, uint32 offset) in si_get_pmu_reg_addr() argument
331 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr()
347 si_setcoreidx(sih, origidx); in si_get_pmu_reg_addr()
349 pmuaddr = SI_ENUM_BASE(sih) + offset; in si_get_pmu_reg_addr()
393 struct si_pub *sih = &sii->pub; in si_buscore_setup() local
405 sii->pub.gcirev = si_corereg(sih, in si_buscore_setup()
406 GCI_CORE_IDX(sih), in si_buscore_setup()
407 GCI_OFFSETOF(sih, gci_corecaps0), 0, 0) & GCI_CAP0_REV_MASK; in si_buscore_setup()
534 si_chipid(si_t *sih) in si_chipid() argument
536 si_info_t *sii = SI_INFO(sih); in si_chipid()
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Dhndlhl.c55 si_lhl_setup(si_t *sih, osl_t *osh) in si_lhl_setup() argument
57 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_lhl_setup()
59 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_2); in si_lhl_setup()
63 LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL); in si_lhl_setup()
64 LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL); in si_lhl_setup()
65 LHL_REG(sih, lhl_top_pwrdn_ctl_adr, LHL_PWRDN_CTL_MASK, LHL_PWRDN_SLEEP_CNT); in si_lhl_setup()
66 LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL); in si_lhl_setup()
67 } else if (BCM4347_CHIP(sih->chip)) { in si_lhl_setup()
68 if (LHL_IS_PSMODE_1(sih)) { in si_lhl_setup()
69 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_1); in si_lhl_setup()
[all …]
Dhndpmu.c102 si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength) in si_sdiod_drive_strength_init() argument
113 UNUSED_PARAMETER(sih); in si_sdiod_drive_strength_init()
119 si_switch_pmu_dependency(si_t *sih, uint mode) in si_switch_pmu_dependency() argument
122 osl_t *osh = si_osh(sih); in si_switch_pmu_dependency()
132 origidx = si_coreidx(sih); in si_switch_pmu_dependency()
133 if (AOB_ENAB(sih)) { in si_switch_pmu_dependency()
134 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_switch_pmu_dependency()
135 cc = si_setcore(sih, CC_CORE_ID, 0); in si_switch_pmu_dependency()
137 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_switch_pmu_dependency()
138 cc = si_setcoreidx(sih, SI_CC_IDX); in si_switch_pmu_dependency()
[all …]
Dhndmem.c46 hndmem_num_banks(si_t *sih, int mem) in hndmem_num_banks() argument
51 osl_t *osh = si_osh(sih); in hndmem_num_banks()
57 savecore = si_coreidx(sih); in hndmem_num_banks()
61 if (!si_setcore(sih, SOCRAM_CORE_ID, 0)) { in hndmem_num_banks()
65 if (sih->gcirev >= 9) { in hndmem_num_banks()
66 gciregs = si_setcore(sih, GCI_CORE_ID, 0); in hndmem_num_banks()
95 si_setcoreidx(sih, savecore); in hndmem_num_banks()
102 hndmem_bank_size(si_t *sih, hndmem_type_t mem, int bank_num) in hndmem_bank_size() argument
107 osl_t *osh = si_osh(sih); in hndmem_bank_size()
113 savecore = si_coreidx(sih); in hndmem_bank_size()
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Dsiutils_priv.h179 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) argument
240 extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
241 extern uint sb_coreid(si_t *sih);
242 extern uint sb_intflag(si_t *sih);
243 extern uint sb_flag(si_t *sih);
244 extern void sb_setint(si_t *sih, int siflag);
245 extern uint sb_corevendor(si_t *sih);
246 extern uint sb_corerev(si_t *sih);
247 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
248 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
[all …]
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/net/wireless/bcmdhd/
Dsiutils.c268 si_get_pmu_reg_addr(si_t *sih, uint32 offset) in si_get_pmu_reg_addr() argument
270 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr()
286 si_setcoreidx(sih, origidx); in si_get_pmu_reg_addr()
332 struct si_pub *sih = &sii->pub; in si_buscore_setup() local
344 sii->pub.gcirev = si_corereg(sih, in si_buscore_setup()
345 GCI_CORE_IDX(sih), in si_buscore_setup()
346 GCI_OFFSETOF(sih, gci_corecaps0), 0, 0) & GCI_CAP0_REV_MASK; in si_buscore_setup()
483 si_chipid(si_t *sih) in si_chipid() argument
485 si_info_t *sii = SI_INFO(sih); in si_chipid()
487 return (sii->chipnew) ? sii->chipnew : sih->chip; in si_chipid()
[all …]
Dsiutils_priv.h163 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) argument
224 extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
225 extern uint sb_coreid(si_t *sih);
226 extern uint sb_intflag(si_t *sih);
227 extern uint sb_flag(si_t *sih);
228 extern void sb_setint(si_t *sih, int siflag);
229 extern uint sb_corevendor(si_t *sih);
230 extern uint sb_corerev(si_t *sih);
231 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
232 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
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