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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
[all …]
/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu/
Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
10 #include "arm-smmu.h"
13 * Tegra194 has three ARM MMU-500 Instances.
16 * non-isochronous HW devices.
20 * The third instance usage is through standard arm-smmu driver itself and
36 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
89 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in nvidia_smmu_tlb_sync()
109 dev_err_ratelimited(smmu->dev, in nvidia_smmu_tlb_sync()
110 "TLB sync timed out -- SMMU may be deadlocked\n"); in nvidia_smmu_tlb_sync()
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Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-iommu.h>
25 #include <linux/dma-mapping.h>
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/kernel/linux/linux-5.10/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
40 select BUILDTIME_TABLE_SORT if MMU
46 select DMA_REMAP if MMU
69 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
70 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dpsb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2007-2011, Intel Corporation.
42 * to the different groups of PowerVR 5-series chip designs
46 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
47 * PowerVR SGX535 - Moorestown - Intel GMA 600
48 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
49 * PowerVR SGX540 - Medfield - Intel Atom Z2460
50 * PowerVR SGX544MP2 - Medfield -
51 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
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/kernel/linux/linux-5.10/drivers/gpu/drm/lima/
Dlima_sched.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
33 return -ENOMEM; in lima_sched_slab_init()
42 if (!--lima_fence_slab_refcnt) { in lima_sched_slab_fini()
62 return f->pipe->base.name; in lima_fence_get_timeline_name()
77 call_rcu(&f->base.rcu, lima_fence_release_rcu); in lima_fence_release()
94 fence->pipe = pipe; in lima_fence_create()
95 dma_fence_init(&fence->base, &lima_fence_ops, &pipe->fence_lock, in lima_fence_create()
96 pipe->fence_context, ++pipe->fence_seqno); in lima_fence_create()
118 task->bos = kmemdup(bos, sizeof(*bos) * num_bos, GFP_KERNEL); in lima_sched_task_init()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
30 interrupt-names = "mhu_lpri_rx",
32 #mbox-cells = <1>;
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Dpmac32-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
41 * init/main.c to make it non-init before enabling DEBUG_FREQ
254 * the above didn't re-enable the DEC */ in pmu_set_cpu_speed()
270 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()
271 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()
298 /* Restore userland MMU context */ in pmu_set_cpu_speed()
299 switch_mmu_context(NULL, current->active_mm, NULL); in pmu_set_cpu_speed()
310 * as soon as interrupts are re-enabled and the generic in pmu_set_cpu_speed()
390 * GPIO space, and the device-tree doesn't help. in read_gpio()
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/kernel/linux/linux-5.10/arch/sparc/include/asm/
Dfloppy_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
76 #if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
106 sun_fdc->dor_82077 = value; in sun_set_dor()
111 return sun_fdc->dir_82077; in sun_read_dir()
122 return sun_fdc->status_82072 & ~STATUS_DMA; in sun_82072_fd_inb()
124 return sun_fdc->data_82072; in sun_82072_fd_inb()
142 sun_fdc->data_82072 = value; in sun_82072_fd_outb()
145 sun_fdc->dcr_82072 = value; in sun_82072_fd_outb()
148 sun_fdc->status_82072 = value; in sun_82072_fd_outb()
162 return sun_fdc->status1_82077; in sun_82077_fd_inb()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
43 - compatible
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/kernel/linux/linux-5.10/drivers/cpuidle/
Dcpuidle-big_little.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * or in the MCPM back-ends.
47 * up and running when the CPU is powered up on cluster wake-up from shutdown.
69 .desc = "ARM little-cluster power down",
75 { .compatible = "arm,idle-state",
86 .exit_latency = 500,
90 .desc = "ARM big-cluster power down",
98 * in power down sequences where caches and MMU may be turned off.
115 * bl_enter_powerdown - Programs CPU to enter the specified state
145 return -ENOMEM; in bl_idle_driver_init()
[all …]
/kernel/linux/linux-5.10/arch/alpha/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
44 The Alpha is a 64-bit general-purpose processor designed and
46 now Hewlett-Packard. The Alpha Linux project has a home page at
52 config MMU config
97 Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
98 Alpha-XL XL-233, XL-266
107 Jensen DECpc 150, DEC 2000 models 300, 500
108 LX164 AlphaPC164-LX
110 Miata Personal Workstation 433/500/600 a/au
117 Ruffian RPX164-2, AlphaPC164-UX, AlphaPC164-BX
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/panfrost/
Dpanfrost_job.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-resv.h>
23 #define JOB_TIMEOUT_MS 500
25 #define job_write(dev, reg, data) writel(data, dev->iomem + (reg))
26 #define job_read(dev, reg) readl(dev->iomem + (reg))
77 switch (f->queue) { in panfrost_fence_get_timeline_name()
79 return "panfrost-js-0"; in panfrost_fence_get_timeline_name()
81 return "panfrost-js-1"; in panfrost_fence_get_timeline_name()
83 return "panfrost-js-2"; in panfrost_fence_get_timeline_name()
97 struct panfrost_job_slot *js = pfdev->js; in panfrost_fence_create()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
[all …]
Domap5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 interrupt-parent = <&wakeupgen>;
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/common/
Dmemory.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
10 #include "../include/hw_ip/mmu/mmu_general.h"
29 * two chunks - one to return as result and a remainder to stay in the list.
42 * alloc_device_memory - allocate device memory
49 * - Allocate the requested size rounded up to 2MB pages
50 * - Return unique handle
55 struct hl_device *hdev = ctx->hdev; in alloc_device_memory()
56 struct hl_vm *vm = &hdev->vm; in alloc_device_memory()
64 page_size = hdev->asic_prop.dram_page_size; in alloc_device_memory()
[all …]
/kernel/linux/linux-5.10/drivers/bus/
Darm-cci.c17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
67 #define DRIVER_NAME "ARM-CCI"
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/goya/
Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
17 #include <linux/io-64-nonatomic-lo-hi.h>
25 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
26 * - MMU
29 * - Range registers (protect the first 512MB)
30 * - MMU (isolation between users)
33 * - Range registers
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/kernel/linux/linux-5.10/Documentation/virt/uml/
Duser_mode_linux_howto_v2.rst1 .. SPDX-License-Identifier: GPL-2.0
25 Most OSes today have built-in support for a number of "fake"
27 User Mode Linux takes this concept to the ultimate extreme - there
30 concepts which map onto something provided by the host - files, sockets,
36 The UML kernel is just a process running on Linux - same as any other
57 * You can run a usermode kernel as a non-root user (you may need to
99 This is extremely easy on Debian - you can do it using debootstrap. It is
100 also easy on OpenWRT - the build process can build UML images. All other
101 distros - YMMV.
114 or by running ``tune2fs -o discard /dev/ubdXX`` will request UML to
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-5.10/Documentation/arm64/
Dsilicon-errata.rst10 so-called "errata", which can cause it to deviate from the architecture
32 cases (e.g. those cases that both require a non-secure workaround *and*
37 Features" -> "ARM errata workarounds via the alternatives framework".
39 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
49 +----------------+-----------------+-----------------+-----------------------------+
53 +----------------+-----------------+-----------------+-----------------------------+
54 +----------------+-----------------+-----------------+-----------------------------+
55 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
56 +----------------+-----------------+-----------------+-----------------------------+
57 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dpci.c846 { 0x00fd, "Quadro FX 330/Quadro NVS 280 PCI-E" },
888 { 0x0173, "GeForce4 MX 440-SE" },
896 { 0x017c, "Quadro4 500 GoGL" },
930 { 0x0202, "GeForce3 Ti 500" },
937 { 0x0222, "GeForce 6200 A-LE" },
997 { 0x032b, "Quadro FX 500/FX 600" },
1168 { 0x06df, "Tesla M2070-Q" },
1325 { 0x0df9, "Quadro 500M" },
1440 { 0x118e, "GeForce GTX 760 (192-bit)" },
1567 return pci_resource_start(pdev->pdev, bar); in nvkm_device_pci_resource_addr()
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