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Searched +full:gcc +full:- +full:sm8250 (Results 1 – 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8250
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
15 power domains on SM8250.
18 - dt-bindings/clock/qcom,gcc-sm8250.h
22 const: qcom,gcc-sm8250
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Dqcom,gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
14 power domains on SDM845/SC7180/SM8150/SM8250.
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
20 dt-bindings/clock/qcom,gpucc-sm8250.h
25 - qcom,sdm845-gpucc
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Dqcom,rpmhcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
20 - qcom,sc7180-rpmh-clk
21 - qcom,sdm845-rpmh-clk
22 - qcom,sm8150-rpmh-clk
23 - qcom,sm8250-rpmh-clk
28 clock-names:
30 - const: xo
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/kernel/linux/linux-5.10/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
417 tristate "SM8150 and SM8250 Display Clock Controller"
421 SM8150 and SM8250 devices.
433 tristate "SM8250 Global Clock Controller"
436 Support for the global clock controller on SM8250 devices.
449 tristate "SM8250 Graphics Clock Controller"
452 Support for the graphics clock controller on SM8250 devices.
466 tristate "SM8250 Video Clock Controller"
470 Support for the video clock controller on SM8250 devices.
484 tristate "High-Frequency PLL (HFPLL) Clock Controller"
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Dgcc-sm8250.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
3627 { .compatible = "qcom,gcc-sm8250" },
3649 * Keep the clocks always-ON in gcc_sm8250_probe()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsm8250.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,osm-l3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <sibis@codeaurora.org>
20 - qcom,sc7180-osm-l3
21 - qcom,sdm845-osm-l3
22 - qcom,sm8150-osm-l3
23 - qcom,sm8250-epss-l3
30 - description: xo clock
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
83 * if yes, then offset gives index in the reg-layout
115 /* set of registers with offsets different per-PHY */
1827 /* struct qmp_phy_cfg - per-PHY initialization config */
1829 /* phy-type - PCIE/UFS/USB */
1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1898 * struct qmp_phy - per-lane phy descriptor
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/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
21 #include "sdhci-pltfm.h"
120 #define INVALID_TUNING_PHASE -1
134 /* Max load for eMMC Vdd-io supply */
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
295 return msm_host->offset; in sdhci_priv_msm_offset()
308 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
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