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Searched refs:radeon_emit (Results 1 – 25 of 51) sorted by relevance

123

/third_party/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c80 radeon_emit(cs, 0); in si_emit_compute()
81 radeon_emit(cs, 0); in si_emit_compute()
82 radeon_emit(cs, 0); in si_emit_compute()
90 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_compute()
91 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_compute()
96 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_compute()
97 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_compute()
103 radeon_emit(cs, bc_va >> 8); in si_emit_compute()
104 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); in si_emit_compute()
116 radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */ in si_emit_compute()
[all …]
Dradv_cs.h48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
56 radeon_emit(cs, value); in radeon_set_config_reg()
65 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
66 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
73 radeon_emit(cs, value); in radeon_set_context_reg()
81 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
82 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
83 radeon_emit(cs, value); in radeon_set_context_reg_idx()
91 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); in radeon_set_context_reg_rmw()
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Dradv_sdma_copy_image.c96 radeon_emit(cmd_buffer->cs, 0x00000000); in radv_sdma_v4_v5_copy_image_to_buffer()
100 radeon_emit(cmd_buffer->cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, in radv_sdma_v4_v5_copy_image_to_buffer()
102 radeon_emit(cmd_buffer->cs, bytes); in radv_sdma_v4_v5_copy_image_to_buffer()
103 radeon_emit(cmd_buffer->cs, 0); in radv_sdma_v4_v5_copy_image_to_buffer()
104 radeon_emit(cmd_buffer->cs, src_address); in radv_sdma_v4_v5_copy_image_to_buffer()
105 radeon_emit(cmd_buffer->cs, src_address >> 32); in radv_sdma_v4_v5_copy_image_to_buffer()
106 radeon_emit(cmd_buffer->cs, dst_address); in radv_sdma_v4_v5_copy_image_to_buffer()
107 radeon_emit(cmd_buffer->cs, dst_address >> 32); in radv_sdma_v4_v5_copy_image_to_buffer()
110 radeon_emit(cmd_buffer->cs, SDMA_NOP_PAD); in radv_sdma_v4_v5_copy_image_to_buffer()
136 radeon_emit(cmd_buffer->cs, 0x00000000); in radv_sdma_v4_v5_copy_image_to_buffer()
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Dradv_sqtt.c201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_start()
202 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_START) | EVENT_INDEX(0)); in radv_emit_thread_trace_start()
245 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_copy_thread_trace_info_regs()
246 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) | COPY_DATA_DST_SEL(COPY_DATA_TC_L2) | in radv_copy_thread_trace_info_regs()
248 radeon_emit(cs, thread_trace_info_regs[i] >> 2); in radv_copy_thread_trace_info_regs()
249 radeon_emit(cs, 0); /* unused */ in radv_copy_thread_trace_info_regs()
250 radeon_emit(cs, (info_va + i * 4)); in radv_copy_thread_trace_info_regs()
251 radeon_emit(cs, (info_va + i * 4) >> 32); in radv_copy_thread_trace_info_regs()
265 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_stop()
266 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_STOP) | EVENT_INDEX(0)); in radv_emit_thread_trace_stop()
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Dradv_cmd_buffer.c383 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); in radv_emit_write_data_packet()
384 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel)); in radv_emit_write_data_packet()
385 radeon_emit(cs, va); in radv_emit_write_data_packet()
386 radeon_emit(cs, va >> 32); in radv_emit_write_data_packet()
692 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_cmd_buffer_trace_emit()
693 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id)); in radv_cmd_buffer_trace_emit()
851 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cmd_buffer_after_draw()
852 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0)); in radv_cmd_buffer_after_draw()
1199 radeon_emit(cs, centroid_priority); in radv_emit_sample_locations()
1200 radeon_emit(cs, centroid_priority >> 32); in radv_emit_sample_locations()
[all …]
Dradv_perfcounter.c36 radeon_emit(cs, shaders & 0x7f); in radv_perfcounter_emit_shaders()
37 radeon_emit(cs, 0xffffffff); in radv_perfcounter_emit_shaders()
45 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_windowed_counters()
46 radeon_emit(cs, EVENT_TYPE(enable ? V_028A90_PERFCOUNTER_START : V_028A90_PERFCOUNTER_STOP) | in radv_emit_windowed_counters()
508 radeon_emit(cs, 0); in radv_emit_select()
526 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_pc_emit_block_instance_read()
527 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) | COPY_DATA_DST_SEL(COPY_DATA_TC_L2) | in radv_pc_emit_block_instance_read()
529 radeon_emit(cs, reg >> 2); in radv_pc_emit_block_instance_read()
530 radeon_emit(cs, 0); /* unused */ in radv_pc_emit_block_instance_read()
531 radeon_emit(cs, va); in radv_pc_emit_block_instance_read()
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/third_party/mesa3d/src/gallium/drivers/r600/
Dcayman_msaa.c168 radeon_emit(cs, cm_sample_locs_8x[0]); in cayman_emit_msaa_sample_locs()
169 radeon_emit(cs, cm_sample_locs_8x[4]); in cayman_emit_msaa_sample_locs()
170 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
171 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
172 radeon_emit(cs, cm_sample_locs_8x[1]); in cayman_emit_msaa_sample_locs()
173 radeon_emit(cs, cm_sample_locs_8x[5]); in cayman_emit_msaa_sample_locs()
174 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
175 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
176 radeon_emit(cs, cm_sample_locs_8x[2]); in cayman_emit_msaa_sample_locs()
177 radeon_emit(cs, cm_sample_locs_8x[6]); in cayman_emit_msaa_sample_locs()
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Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_vgt_streamout()
170 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); in r600_flush_vgt_streamout()
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in r600_flush_vgt_streamout()
173 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ in r600_flush_vgt_streamout()
174 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ in r600_flush_vgt_streamout()
175 radeon_emit(cs, 0); in r600_flush_vgt_streamout()
176 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ in r600_flush_vgt_streamout()
177 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ in r600_flush_vgt_streamout()
178 radeon_emit(cs, 4); /* poll interval */ in r600_flush_vgt_streamout()
201 radeon_emit(cs, (t[i]->b.buffer_offset + in r600_emit_streamout_begin()
[all …]
Dr600_hw_context.c125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
126 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
131 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
145 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in r600_flush_emit()
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
151 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in r600_flush_emit()
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
165 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_flush_emit()
[all …]
Dr600_cs.h123 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
124 radeon_emit(cs, reloc); in r600_emit_reloc()
132 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
133 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
139 radeon_emit(cs, value); in radeon_set_config_reg()
146 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
147 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
153 radeon_emit(cs, value); in radeon_set_context_reg()
162 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
163 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
[all …]
Devergreen_hw_context.c69 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize)); in evergreen_dma_copy_buffer()
70 radeon_emit(cs, dst_offset & 0xffffffff); in evergreen_dma_copy_buffer()
71 radeon_emit(cs, src_offset & 0xffffffff); in evergreen_dma_copy_buffer()
72 radeon_emit(cs, (dst_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
129 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in evergreen_cp_dma_clear_buffer()
130 radeon_emit(cs, clear_value); /* DATA [31:0] */ in evergreen_cp_dma_clear_buffer()
131 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */ in evergreen_cp_dma_clear_buffer()
132 radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */ in evergreen_cp_dma_clear_buffer()
133 radeon_emit(cs, (offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */ in evergreen_cp_dma_clear_buffer()
[all …]
Devergreen_state.c988 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs)); in evergreen_emit_config_state()
989 radeon_emit(cs, 0); in evergreen_emit_config_state()
990 radeon_emit(cs, 0); in evergreen_emit_config_state()
992 radeon_emit(cs, a->sq_gpr_resource_mgmt_1); in evergreen_emit_config_state()
993 radeon_emit(cs, a->sq_gpr_resource_mgmt_2); in evergreen_emit_config_state()
994 radeon_emit(cs, a->sq_gpr_resource_mgmt_3); in evergreen_emit_config_state()
1688 radeon_emit(cs, S_028C00_LAST_PIXEL(1) | in evergreen_emit_msaa_state()
1690 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | in evergreen_emit_msaa_state()
1698 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ in evergreen_emit_msaa_state()
1699 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ in evergreen_emit_msaa_state()
[all …]
Dr600_state.c281 radeon_emit(cs, fui(offset_scale)); in r600_emit_polygon_offset()
282 radeon_emit(cs, fui(offset_units)); in r600_emit_polygon_offset()
283 radeon_emit(cs, fui(offset_scale)); in r600_emit_polygon_offset()
284 radeon_emit(cs, fui(offset_units)); in r600_emit_polygon_offset()
1308 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */ in r600_emit_msaa_state()
1309 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */ in r600_emit_msaa_state()
1317 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ in r600_emit_msaa_state()
1318 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ in r600_emit_msaa_state()
1323 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ in r600_emit_msaa_state()
1324 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ in r600_emit_msaa_state()
[all …]
Devergreen_compute.c637 radeon_emit(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */ in evergreen_emit_dispatch()
638 radeon_emit(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */ in evergreen_emit_dispatch()
639 radeon_emit(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */ in evergreen_emit_dispatch()
645 radeon_emit(cs, info->block[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */ in evergreen_emit_dispatch()
646 radeon_emit(cs, info->block[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */ in evergreen_emit_dispatch()
647 radeon_emit(cs, info->block[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */ in evergreen_emit_dispatch()
661 radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, render_cond_bit)); in evergreen_emit_dispatch()
662 radeon_emit(cs, indirect_grid[0]); in evergreen_emit_dispatch()
663 radeon_emit(cs, indirect_grid[1]); in evergreen_emit_dispatch()
664 radeon_emit(cs, indirect_grid[2]); in evergreen_emit_dispatch()
[all …]
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_streamout.c225 radeon_emit(PKT3(PKT3_WRITE_DATA, 3, 0)); in si_flush_vgt_streamout()
226 radeon_emit(S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME)); in si_flush_vgt_streamout()
227 radeon_emit(R_0300FC_CP_STRMOUT_CNTL >> 2); in si_flush_vgt_streamout()
228 radeon_emit(0); in si_flush_vgt_streamout()
229 radeon_emit(0); in si_flush_vgt_streamout()
238 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_vgt_streamout()
239 radeon_emit(EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); in si_flush_vgt_streamout()
241 radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_flush_vgt_streamout()
242 radeon_emit(WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ in si_flush_vgt_streamout()
243 radeon_emit(reg_strmout_cntl >> 2); /* register */ in si_flush_vgt_streamout()
[all …]
Dsi_sdma_copy_image.c139 radeon_emit(CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, in si_sdma_v4_v5_copy_texture()
142 radeon_emit(bytes); in si_sdma_v4_v5_copy_texture()
143 radeon_emit(0); in si_sdma_v4_v5_copy_texture()
144 radeon_emit(src_address); in si_sdma_v4_v5_copy_texture()
145 radeon_emit(src_address >> 32); in si_sdma_v4_v5_copy_texture()
146 radeon_emit(dst_address); in si_sdma_v4_v5_copy_texture()
147 radeon_emit(dst_address >> 32); in si_sdma_v4_v5_copy_texture()
176 radeon_emit( in si_sdma_v4_v5_copy_texture()
183 radeon_emit((uint32_t)tiled_address | (tiled->surface.tile_swizzle << 8)); in si_sdma_v4_v5_copy_texture()
184 radeon_emit((uint32_t)(tiled_address >> 32)); in si_sdma_v4_v5_copy_texture()
[all …]
Dsi_build_pm4.h61 #define radeon_emit(value) __cs_buf[__cs_num++] = (value) macro
79 radeon_emit(PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
80 radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
85 radeon_emit(value); \
91 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
92 radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
97 radeon_emit(value); \
108 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
109 radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2 | ((idx) << 28)); \
110 radeon_emit(value); \
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Dsi_gfx_cs.c121 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_gfx_cs()
122 radeon_emit(EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); in si_flush_gfx_cs()
571 radeon_emit(PKT3(PKT3_NOP, 0, 0)); in si_trace_emit()
572 radeon_emit(AC_ENCODE_TRACE_POINT(trace_id)); in si_trace_emit()
593 radeon_emit(PKT3(PKT3_ACQUIRE_MEM, 5, 0)); in si_emit_surface_sync()
594 radeon_emit(cp_coher_cntl); /* CP_COHER_CNTL */ in si_emit_surface_sync()
595 radeon_emit(0xffffffff); /* CP_COHER_SIZE */ in si_emit_surface_sync()
596 radeon_emit(0xffffff); /* CP_COHER_SIZE_HI */ in si_emit_surface_sync()
597 radeon_emit(0); /* CP_COHER_BASE */ in si_emit_surface_sync()
598 radeon_emit(0); /* CP_COHER_BASE_HI */ in si_emit_surface_sync()
[all …]
Dsi_fence.c111 radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cp_release_mem()
112 radeon_emit(EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); in si_cp_release_mem()
113 radeon_emit(scratch->gpu_address); in si_cp_release_mem()
114 radeon_emit(scratch->gpu_address >> 32); in si_cp_release_mem()
120 radeon_emit(PKT3(PKT3_RELEASE_MEM, ctx->gfx_level >= GFX9 ? 6 : 5, 0)); in si_cp_release_mem()
121 radeon_emit(op); in si_cp_release_mem()
122 radeon_emit(sel); in si_cp_release_mem()
123 radeon_emit(va); /* address lo */ in si_cp_release_mem()
124 radeon_emit(va >> 32); /* address hi */ in si_cp_release_mem()
125 radeon_emit(new_fence); /* immediate data lo */ in si_cp_release_mem()
[all …]
Dsi_compute.c385 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
386 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
403 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
404 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
418 radeon_emit(bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */ in si_emit_initial_compute_regs()
419 radeon_emit(S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */ in si_emit_initial_compute_regs()
434 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
435 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
436 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
437 radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); in si_emit_initial_compute_regs()
[all …]
Dsi_cp_dma.c104 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_cp_dma()
105 radeon_emit(header); in si_emit_cp_dma()
106 radeon_emit(src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
107 radeon_emit(src_va >> 32); /* SRC_ADDR_HI [31:0] */ in si_emit_cp_dma()
108 radeon_emit(dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
109 radeon_emit(dst_va >> 32); /* DST_ADDR_HI [31:0] */ in si_emit_cp_dma()
110 radeon_emit(command); in si_emit_cp_dma()
114 radeon_emit(PKT3(PKT3_CP_DMA, 4, 0)); in si_emit_cp_dma()
115 radeon_emit(src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
116 radeon_emit(header); /* SRC_ADDR_HI [15:0] + flags. */ in si_emit_cp_dma()
[all …]
Dsi_sqtt.c223 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_thread_trace_start()
224 radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_START) | EVENT_INDEX(0)); in si_emit_thread_trace_start()
270 radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); in si_copy_thread_trace_info_regs()
271 radeon_emit(COPY_DATA_SRC_SEL(COPY_DATA_PERF) | in si_copy_thread_trace_info_regs()
274 radeon_emit(thread_trace_info_regs[i] >> 2); in si_copy_thread_trace_info_regs()
275 radeon_emit(0); /* unused */ in si_copy_thread_trace_info_regs()
276 radeon_emit((info_va + i * 4)); in si_copy_thread_trace_info_regs()
277 radeon_emit((info_va + i * 4) >> 32); in si_copy_thread_trace_info_regs()
298 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_thread_trace_stop()
299 radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_STOP) | EVENT_INDEX(0)); in si_emit_thread_trace_stop()
[all …]
Dradeon_vcn.c34 radeon_emit(cs, RADEON_VCN_SIGNATURE_SIZE); in rvcn_sq_header()
35 radeon_emit(cs, RADEON_VCN_SIGNATURE); in rvcn_sq_header()
37 radeon_emit(cs, 0); in rvcn_sq_header()
39 radeon_emit(cs, 0); in rvcn_sq_header()
42 radeon_emit(cs, RADEON_VCN_ENGINE_INFO_SIZE); in rvcn_sq_header()
43 radeon_emit(cs, RADEON_VCN_ENGINE_INFO); in rvcn_sq_header()
44 radeon_emit(cs, enc ? RADEON_VCN_ENGINE_TYPE_ENCODE in rvcn_sq_header()
46 radeon_emit(cs, 0); in rvcn_sq_header()
Dsi_perfcounter.c92 radeon_emit(shaders & 0x7f); in si_pc_emit_shaders()
93 radeon_emit(0xffffffff); in si_pc_emit_shaders()
114 radeon_emit(selectors[idx] | regs->select_or); in si_pc_emit_select()
119 radeon_emit(0); in si_pc_emit_select()
135 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_start()
136 radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0)); in si_pc_emit_start()
153 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
154 radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0)); in si_pc_emit_stop()
157 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_pc_emit_stop()
158 radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0)); in si_pc_emit_stop()
[all …]
Dsi_state_draw.cpp442 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0)); in si_cp_dma_prefetch_inline()
443 radeon_emit(header); in si_cp_dma_prefetch_inline()
444 radeon_emit(address); /* SRC_ADDR_LO [31:0] */ in si_cp_dma_prefetch_inline()
445 radeon_emit(address >> 32); /* SRC_ADDR_HI [31:0] */ in si_cp_dma_prefetch_inline()
446 radeon_emit(address); /* DST_ADDR_LO [31:0] */ in si_cp_dma_prefetch_inline()
447 radeon_emit(address >> 32); /* DST_ADDR_HI [31:0] */ in si_cp_dma_prefetch_inline()
448 radeon_emit(command); in si_cp_dma_prefetch_inline()
819 radeon_emit(offchip_layout); in si_emit_derived_tess_state()
820 radeon_emit(tcs_out_offsets); in si_emit_derived_tess_state()
821 radeon_emit(tcs_out_layout); in si_emit_derived_tess_state()
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