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/kernel/linux/linux-5.10/drivers/net/phy/
Dbroadcom.c49 if (rc < 0) in bcm54xx_config_clock_delay()
65 if (rc < 0) in bcm54xx_config_clock_delay()
68 return 0; in bcm54xx_config_clock_delay()
83 return 0; in bcm54210e_config_init()
100 if (err < 0) in bcm54612e_config_init()
104 return 0; in bcm54612e_config_init()
113 return 0; in bcm54616s_config_init()
118 if (val < 0) in bcm54616s_config_init()
124 if (rc < 0) in bcm54616s_config_init()
129 if (val < 0) in bcm54616s_config_init()
[all …]
Dbcm7xxx.c20 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
21 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
22 #define MII_BCM7XXX_100TX_DISC 0x14
23 #define MII_BCM7XXX_AUX_MODE 0x1d
25 #define MII_BCM7XXX_TEST 0x1f
27 #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
28 #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
29 #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
30 #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
31 #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
[all …]
Dsmsc.c28 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ 0x0001
32 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ 0x8000
33 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ 0x4000
34 #define SPECIAL_CTRL_STS_AMDIX_STATE_ 0x2000
54 u16 intmask = 0; in smsc_phy_config_intr()
65 return rc < 0 ? rc : 0; in smsc_phy_config_intr()
72 return rc < 0 ? rc : 0; in smsc_phy_ack_interrupt()
81 return 0; in smsc_phy_config_init()
85 if (rc < 0) in smsc_phy_config_init()
91 if (rc < 0) in smsc_phy_config_init()
[all …]
Ddp83848.c11 #define TI_DP83848C_PHY_ID 0x20005ca0
12 #define TI_DP83620_PHY_ID 0x20005ce0
13 #define NS_DP83848C_PHY_ID 0x20005c90
14 #define TLK10X_PHY_ID 0x2000a210
17 #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
18 #define DP83848_MISR 0x12 /* MII Interrupt Status Register */
21 #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
25 #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
44 return err < 0 ? err : 0; in dp83848_ack_interrupt()
52 if (control < 0) in dp83848_config_intr()
[all …]
Dlxt.c36 #define MII_LXT970_IER_IEN 0x0002
47 #define MII_LXT971_IER_IEN 0x00f2
65 if (err < 0) in lxt970_ack_interrupt()
70 if (err < 0) in lxt970_ack_interrupt()
73 return 0; in lxt970_ack_interrupt()
81 return phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
86 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
94 if (err < 0) in lxt971_ack_interrupt()
97 return 0; in lxt971_ack_interrupt()
105 return phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
[all …]
Ddp83822.c16 #define DP83822_PHY_ID 0x2000a240
17 #define DP83825S_PHY_ID 0x2000a140
18 #define DP83825I_PHY_ID 0x2000a150
19 #define DP83825CM_PHY_ID 0x2000a160
20 #define DP83825CS_PHY_ID 0x2000a170
21 #define DP83826C_PHY_ID 0x2000a130
22 #define DP83826NC_PHY_ID 0x2000a110
24 #define DP83822_DEVADDR 0x1f
26 #define MII_DP83822_CTRL_2 0x0a
27 #define MII_DP83822_PHYSTS 0x10
[all …]
Dbcm-cygnus.c18 #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
26 if (rc < 0) in bcm_cygnus_afe_config()
30 rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); in bcm_cygnus_afe_config()
31 if (rc < 0) in bcm_cygnus_afe_config()
35 rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); in bcm_cygnus_afe_config()
36 if (rc < 0) in bcm_cygnus_afe_config()
40 rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); in bcm_cygnus_afe_config()
41 if (rc < 0) in bcm_cygnus_afe_config()
45 rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); in bcm_cygnus_afe_config()
[all …]
Dax88796b.c13 #define PHY_ID_ASIX_AX88796B 0x003b1841
28 * Returns: 0 on success, < 0 on failure
35 ret = phy_write(phydev, MII_BMCR, 0); in asix_soft_reset()
36 if (ret < 0) in asix_soft_reset()
45 .phy_id_mask = 0xfffffff0,
53 { PHY_ID_ASIX_AX88796B, 0xfffffff0 },
Damd.c16 #define PHY_ID_AM79C874 0x0022561b
19 #define MII_AM79C_IR_EN_LINK 0x0400 /* IR enable Linkstate */
20 #define MII_AM79C_IR_EN_ANEG 0x0100 /* IR enable Aneg Complete */
32 if (err < 0) in am79c_ack_interrupt()
36 if (err < 0) in am79c_ack_interrupt()
39 return 0; in am79c_ack_interrupt()
44 return 0; in am79c_config_init()
54 err = phy_write(phydev, MII_AM79C_IR, 0); in am79c_config_intr()
62 .phy_id_mask = 0xfffffff0,
72 { PHY_ID_AM79C874, 0xfffffff0 },
/kernel/linux/linux-6.6/drivers/net/phy/
Dbroadcom.c45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()
67 if (rc < 0) in bcm54xx_config_clock_delay()
83 if (rc < 0) in bcm54xx_config_clock_delay()
86 return 0; in bcm54xx_config_clock_delay()
101 return 0; in bcm54210e_config_init()
118 if (err < 0) in bcm54612e_config_init()
122 return 0; in bcm54612e_config_init()
131 return 0; in bcm54616s_config_init()
136 if (val < 0) in bcm54616s_config_init()
142 if (rc < 0) in bcm54616s_config_init()
[all …]
Dbcm7xxx.c20 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
21 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
22 #define MII_BCM7XXX_100TX_DISC 0x14
23 #define MII_BCM7XXX_AUX_MODE 0x1d
25 #define MII_BCM7XXX_TEST 0x1f
27 #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
28 #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
29 #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
30 #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
31 #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
[all …]
Ddp83848.c11 #define TI_DP83848C_PHY_ID 0x20005ca0
12 #define TI_DP83620_PHY_ID 0x20005ce0
13 #define NS_DP83848C_PHY_ID 0x20005c90
14 #define TLK10X_PHY_ID 0x2000a210
17 #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
18 #define DP83848_MISR 0x12 /* MII Interrupt Status Register */
21 #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
25 #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
58 return err < 0 ? err : 0; in dp83848_ack_interrupt()
66 if (control < 0) in dp83848_config_intr()
[all …]
Dsmsc.c30 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ 0x0001
34 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ 0x8000
35 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ 0x4000
36 #define SPECIAL_CTRL_STS_AMDIX_STATE_ 0x2000
63 return rc < 0 ? rc : 0; in smsc_phy_ack_interrupt()
78 rc = phy_write(phydev, MII_LAN83C185_IM, 0); in smsc_phy_config_intr()
85 return rc < 0 ? rc : 0; in smsc_phy_config_intr()
106 if (irq_status < 0) { in smsc_phy_handle_interrupt()
127 return 0; in smsc_phy_config_init()
140 if (rc < 0) in smsc_phy_reset()
[all …]
Dlxt.c36 #define MII_LXT970_IER_IEN 0x0002
49 #define MII_LXT971_IER_IEN 0x00f2
52 #define MII_LXT971_ISR_MASK 0x00f0
68 if (err < 0) in lxt970_ack_interrupt()
73 if (err < 0) in lxt970_ack_interrupt()
76 return 0; in lxt970_ack_interrupt()
90 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
108 if (irq_status < 0) { in lxt970_handle_interrupt()
114 if (irq_status < 0) { in lxt970_handle_interrupt()
129 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
[all …]
Ddp83822.c16 #define DP83822_PHY_ID 0x2000a240
17 #define DP83825S_PHY_ID 0x2000a140
18 #define DP83825I_PHY_ID 0x2000a150
19 #define DP83825CM_PHY_ID 0x2000a160
20 #define DP83825CS_PHY_ID 0x2000a170
21 #define DP83826C_PHY_ID 0x2000a130
22 #define DP83826NC_PHY_ID 0x2000a110
24 #define DP83822_DEVADDR 0x1f
26 #define MII_DP83822_CTRL_2 0x0a
27 #define MII_DP83822_PHYSTS 0x10
[all …]
Dbcm-cygnus.c18 #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
26 if (rc < 0) in bcm_cygnus_afe_config()
30 rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); in bcm_cygnus_afe_config()
31 if (rc < 0) in bcm_cygnus_afe_config()
35 rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); in bcm_cygnus_afe_config()
36 if (rc < 0) in bcm_cygnus_afe_config()
40 rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); in bcm_cygnus_afe_config()
41 if (rc < 0) in bcm_cygnus_afe_config()
45 rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); in bcm_cygnus_afe_config()
[all …]
Damd.c16 #define PHY_ID_AM79C874 0x0022561b
19 #define MII_AM79C_IR_EN_LINK 0x0400 /* IR enable Linkstate */
20 #define MII_AM79C_IR_EN_ANEG 0x0100 /* IR enable Aneg Complete */
24 #define MII_AM79C_IR_ANEG_DONE BIT(0)
36 if (err < 0) in am79c_ack_interrupt()
40 if (err < 0) in am79c_ack_interrupt()
43 return 0; in am79c_ack_interrupt()
48 return 0; in am79c_config_init()
62 err = phy_write(phydev, MII_AM79C_IR, 0); in am79c_config_intr()
77 if (irq_status < 0) { in am79c_handle_interrupt()
[all …]
/kernel/linux/linux-5.10/drivers/net/
Dsungem_phy.c41 { 0, 0, 0 }, /* No link */
42 { 0, 0, 0 }, /* 10BT Half Duplex */
43 { 1, 0, 0 }, /* 10BT Full Duplex */
44 { 0, 1, 0 }, /* 100BT Half Duplex */
45 { 0, 1, 0 }, /* 100BT Half Duplex */
46 { 1, 1, 0 }, /* 100BT Full Duplex*/
47 { 1, 0, 1 }, /* 1000BT */
48 { 1, 0, 1 }, /* 1000BT */
85 if ((val & BMCR_RESET) == 0) in reset_one_mii_phy()
89 if ((val & BMCR_ISOLATE) && limit > 0) in reset_one_mii_phy()
[all …]
/kernel/linux/linux-6.6/drivers/net/
Dsungem_phy.c37 { 0, 0, 0 }, /* No link */
38 { 0, 0, 0 }, /* 10BT Half Duplex */
39 { 1, 0, 0 }, /* 10BT Full Duplex */
40 { 0, 1, 0 }, /* 100BT Half Duplex */
41 { 0, 1, 0 }, /* 100BT Half Duplex */
42 { 1, 1, 0 }, /* 100BT Full Duplex*/
43 { 1, 0, 1 }, /* 1000BT */
44 { 1, 0, 1 }, /* 1000BT */
81 if ((val & BMCR_RESET) == 0) in reset_one_mii_phy()
85 if ((val & BMCR_ISOLATE) && limit > 0) in reset_one_mii_phy()
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/netfilter_bridge/
Debt_mark_t.h10 * action 0xfffffff0, the result will look ok for older
12 #define MARK_SET_VALUE (0xfffffff0)
13 #define MARK_OR_VALUE (0xffffffe0)
14 #define MARK_AND_VALUE (0xffffffd0)
15 #define MARK_XOR_VALUE (0xffffffc0)
/kernel/linux/linux-6.6/include/uapi/linux/netfilter_bridge/
Debt_mark_t.h10 * action 0xfffffff0, the result will look ok for older
12 #define MARK_SET_VALUE (0xfffffff0)
13 #define MARK_OR_VALUE (0xffffffe0)
14 #define MARK_AND_VALUE (0xffffffd0)
15 #define MARK_XOR_VALUE (0xffffffc0)
/kernel/linux/linux-5.10/drivers/net/phy/mscc/
Dmscc_main.c103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
125 return 0; in vsc85xx_get_sset_count()
138 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()
150 if (val < 0) in vsc85xx_get_stat()
168 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_stats()
199 return 0; in vsc85xx_mdix_get()
221 reg_val = 0; in vsc85xx_mdix_set()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-ixp4xx/include/mach/
Dcpu.h16 /* Processor id value in CP15 Register 0 */
17 #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
18 #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
20 #define IXP43X_PROCESSOR_ID_VALUE 0x69054040
21 #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
23 #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
24 #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
26 #define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
/kernel/linux/linux-6.6/arch/mips/loongson2ef/common/cs5536/
Dcs5536_ide.c17 u32 hi = 0, lo = value; in pci_ide_write_reg()
23 lo |= (0x03 << 4); in pci_ide_write_reg()
25 lo &= ~(0x03 << 4); in pci_ide_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
55 hi = 0x60000000 | ((value & 0x000ff000) >> 12); in pci_ide_write_reg()
[all …]
/kernel/linux/linux-5.10/arch/mips/loongson2ef/common/cs5536/
Dcs5536_ide.c17 u32 hi = 0, lo = value; in pci_ide_write_reg()
23 lo |= (0x03 << 4); in pci_ide_write_reg()
25 lo &= ~(0x03 << 4); in pci_ide_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
55 hi = 0x60000000 | ((value & 0x000ff000) >> 12); in pci_ide_write_reg()
[all …]

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