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/kernel/linux/linux-6.6/arch/arm/include/asm/hardware/
Dcp14.h35 * Available only in DBGv7.1
45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
[all …]
/kernel/linux/linux-5.10/arch/arm/include/asm/hardware/
Dcp14.h35 * Available only in DBGv7.1
45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/hid/tests/
Dtest_multitouch.py24 return 1 << x
29 "SLOT_IS_CONTACTID": BIT(1),
109 input_info=(BusType.USB, 1, 2), argument
130 self.max_contacts = 1
155 self.scantime += 1
179 return (1, [])
187 return (1, [])
190 return (1, [])
198 return 1
206 return 1
[all …]
Dtest_tablet.py374 input_info=(BusType.USB, 1, 2), argument
400 return (1, [])
408 return (1, [])
410 return (1, [])
414 return 1
422 return 1
424 return 1
448 events = events[idx + 1 :]
477 p.x += 1
478 p.y -= 1
[all …]
/kernel/linux/linux-5.10/arch/arm/mm/
Dproc-v7.S32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
57 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
83 ALT_UP_B(1f)
85 1: dcache_line_size r2, r3
86 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
[all …]
Dproc-v6.S22 #define TTB_C (1 << 0)
23 #define TTB_S (1 << 1)
24 #define TTB_IMP (1 << 2)
26 #define TTB_RGN_WBWA (1 << 3)
39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
Dproc-arm740.S37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
77 movs r3, r3, lsr #1
78 bne 1b @ count not zero r-shift
[all …]
/kernel/linux/linux-6.6/arch/arm/mm/
Dproc-v7.S34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
59 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
85 ALT_UP_B(1f)
87 1: dcache_line_size r2, r3
88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
[all …]
Dproc-v6.S22 #define TTB_C (1 << 0)
23 #define TTB_S (1 << 1)
24 #define TTB_IMP (1 << 2)
26 #define TTB_RGN_WBWA (1 << 3)
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
Dproc-arm740.S37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
77 movs r3, r3, lsr #1
78 bne 1b @ count not zero r-shift
[all …]
/kernel/liteos_a/arch/arm/arm/include/
Darm.h8 * 1. Redistributions of source code must retain the above copyright notice, this list of
42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val)); in OsArmReadSctlr()
48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val)); in OsArmWriteSctlr()
55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val)); in OsArmReadActlr()
61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val)); in OsArmWriteActlr()
68 __asm__ volatile("mrc p15, 0, %0, c1,c0,2" : "=r"(val)); in OsArmReadCpacr()
74 __asm__ volatile("mcr p15, 0, %0, c1,c0,2" ::"r"(val)); in OsArmWriteCpacr()
81 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr()
87 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val)); in OsArmWriteTtbr()
94 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr0()
[all …]
Dlos_hw_cpu.h8 * 1. Redistributions of source code must retain the above copyright notice, this list of
90 * Identification registers (c0)
92 #define MIDR CP15_REG(c0, 0, c0, 0) /* Main ID Register */
93 #define MPIDR CP15_REG(c0, 0, c0, 5) /* Multiprocessor Affinity Register */
94 #define CCSIDR CP15_REG(c0, 1, c0, 0) /* Cache Size ID Registers */
95 #define CLIDR CP15_REG(c0, 1, c0, 1) /* Cache Level ID Register */
96 #define VPIDR CP15_REG(c0, 4, c0, 0) /* Virtualization Processor ID Register */
97 #define VMPIDR CP15_REG(c0, 4, c0, 5) /* Virtualization Multiprocessor ID Register …
102 #define SCTLR CP15_REG(c1, 0, c0, 0) /* System Control Register */
103 #define ACTLR CP15_REG(c1, 0, c0, 1) /* Auxiliary Control Register */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s51 .b32 #cmd_query_get + 0x00000 ~1
154 shl b32 $r5 $r4 1
165 mov $r4 1
173 shl b32 $r15 $r4 1
183 mov $r6 #dma_count - 1
189 sub b32 $r6 1
264 cmpu b32 $r6 1
276 or $r2 1
294 mov $r4 1
353 xor $r3 1
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s51 .b32 #cmd_query_get + 0x00000 ~1
154 shl b32 $r5 $r4 1
165 mov $r4 1
173 shl b32 $r15 $r4 1
183 mov $r6 #dma_count - 1
189 sub b32 $r6 1
264 cmpu b32 $r6 1
276 or $r2 1
294 mov $r4 1
353 xor $r3 1
[all …]
/kernel/linux/linux-5.10/arch/arm/include/debug/
Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
32 subs \rd, \rd, #1
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
59 subs \rd, \rd, #1
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
[all …]
/kernel/linux/linux-6.6/arch/arm/include/debug/
Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
32 subs \rd, \rd, #1
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
59 subs \rd, \rd, #1
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
[all …]
/kernel/linux/linux-5.10/arch/arm/kernel/
Dhyp-stub.S114 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
122 THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
123 ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
124 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
126 mrc p15, 4, r7, c1, c1, 1 @ HDCR
128 mcr p15, 4, r7, c1, c1, 1 @ HDCR
131 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
132 orr r7, #(1 << 5) @ CP15 barriers enabled
135 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
137 mrc p15, 0, r7, c0, c0, 0 @ MIDR
[all …]
/kernel/linux/linux-6.6/arch/arm/kernel/
Dhyp-stub.S116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
124 THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
125 ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
128 mrc p15, 4, r7, c1, c1, 1 @ HDCR
130 mcr p15, 4, r7, c1, c1, 1 @ HDCR
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
134 orr r7, #(1 << 5) @ CP15 barriers enabled
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
[all …]
/kernel/linux/linux-6.6/arch/s390/crypto/
Dchacha-s390.S21 .long 1,0,0,0
26 .long 0,1,2,3
100 VREPF XB1,K1,1
105 VREPF XD1,K3,1
111 VREPF XC1,K2,1
402 la %r1,1(%r1)
442 #define C0 %v2 macro
508 VAF D1,K3,T1 # K[3]+1
514 VLR C0,K2
545 VAF C0,C0,D0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/compressed/
Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
142 tst \reg, #(1 << 5) @ CP15BEN bit set?
144 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
162 ldrb \tmp2, [\tmp1, #1]
191 * These 7 nops along with the 1 nop immediately below for
213 W(b) 1f
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-sunxi/
Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
/kernel/linux/linux-6.6/arch/arm/mach-sunxi/
Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dsleep44xx.S47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
127 tst r0, #(1 << 18)
128 mrcne p15, 0, r0, c1, c0, 1
129 bicne r0, r0, #(1 << 6) @ Disable SMP bit
130 mcrne p15, 0, r0, c1, c0, 1
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dsleep44xx.S47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
127 tst r0, #(1 << 18)
128 mrcne p15, 0, r0, c1, c0, 1
129 bicne r0, r0, #(1 << 6) @ Disable SMP bit
130 mcrne p15, 0, r0, c1, c0, 1
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/compressed/
Dhead.S32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
140 tst \reg, #(1 << 5) @ CP15BEN bit set?
142 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
160 ldrb \tmp2, [\tmp1, #1]
170 sub ip, r1, ip, ror #1 @ poor man's kaslr seed, will
201 * These 7 nops along with the 1 nop immediately below for
[all …]

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