| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pwm.h>
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable()
47 dev_err(chip->dev, "error reading PWM#%u control\n", in stmpe_24xx_pwm_enable()
48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
54 ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value); in stmpe_24xx_pwm_enable()
56 dev_err(chip->dev, "error writing PWM#%u control\n", in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
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| D | pwm-pca9685.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for PCA9685 16-channel 12-bit PWM LED controller
8 * based on the pwm-twl-led.c driver
18 #include <linux/pwm.h>
27 * one channel affects the period of all 16 PWM outputs!
28 * However, the ratio between each configured duty cycle and the chip-wide
95 mutex_lock(&pca->lock); in pca9685_pwm_test_and_set_inuse()
101 if (!bitmap_empty(pca->pwms_inuse, PCA9685_MAXCHAN)) { in pca9685_pwm_test_and_set_inuse()
110 if (test_bit(PCA9685_MAXCHAN, pca->pwms_inuse)) { in pca9685_pwm_test_and_set_inuse()
115 is_inuse = test_and_set_bit(pwm_idx, pca->pwms_inuse); in pca9685_pwm_test_and_set_inuse()
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| D | pwm-pxa.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-pxa.c
5 * simple driver for PWM (Pulse Width Modulator) controller
7 * 2008-02-13 initial version
18 #include <linux/pwm.h>
26 /* PWM has_secondary_pwm? */
27 { "pxa25x-pwm", 0 },
28 { "pxa27x-pwm", HAS_SECONDARY_PWM },
29 { "pxa168-pwm", 0 },
30 { "pxa910-pwm", 0 },
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| D | pwm-zx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pwm.h>
42 unsigned int offset) in zx_pwm_readl() argument
44 return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); in zx_pwm_readl()
48 unsigned int offset, u32 value) in zx_pwm_writel() argument
50 writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset); in zx_pwm_writel()
54 unsigned int offset, u32 mask, u32 value) in zx_pwm_set_mask() argument
58 data = zx_pwm_readl(zpc, hwpwm, offset); in zx_pwm_set_mask()
61 zx_pwm_writel(zpc, hwpwm, offset, data); in zx_pwm_set_mask()
64 static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in zx_pwm_get_state() argument
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| D | pwm-atmel.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
31 #include <linux/pwm.h>
34 /* The following is global registers for PWM controller */
42 /* The following register is PWM channel related registers */
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| D | pwm-lp3943.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI/National Semiconductor LP3943 PWM driver
15 #include <linux/pwm.h>
36 struct lp3943_platform_data *pdata = lp3943_pwm->pdata; in lp3943_pwm_request_map()
37 struct lp3943 *lp3943 = lp3943_pwm->lp3943; in lp3943_pwm_request_map()
39 int i, offset; in lp3943_pwm_request_map() local
43 return ERR_PTR(-ENOMEM); in lp3943_pwm_request_map()
45 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
46 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
48 for (i = 0; i < pwm_map->num_outputs; i++) { in lp3943_pwm_request_map()
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| D | pwm-berlin.c | 2 * Marvell Berlin PWM driver
6 * Author: Antoine Tenart <antoine.tenart@free-electrons.com>
18 #include <linux/pwm.h>
60 unsigned int channel, unsigned long offset) in berlin_pwm_readl() argument
62 return readl_relaxed(chip->base + channel * 0x10 + offset); in berlin_pwm_readl()
67 unsigned long offset) in berlin_pwm_writel() argument
69 writel_relaxed(value, chip->base + channel * 0x10 + offset); in berlin_pwm_writel()
72 static int berlin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in berlin_pwm_request() argument
78 return -ENOMEM; in berlin_pwm_request()
80 return pwm_set_chip_data(pwm, channel); in berlin_pwm_request()
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| D | pwm-mediatek.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/pwm.h>
23 /* PWM registers and bits definitions */
42 * struct pwm_mediatek_chip - struct representing PWM chip
43 * @chip: linux PWM chip representation
44 * @regs: base address of PWM chip
46 * @clk_main: the clock used by PWM core
47 * @clk_pwms: the clock used by each PWM channel
71 struct pwm_device *pwm) in pwm_mediatek_clk_enable() argument
76 ret = clk_prepare_enable(pc->clk_top); in pwm_mediatek_clk_enable()
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| D | pwm-rcar.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car PWM Timer driver
8 * - The hardware cannot generate a 0% duty cycle.
20 #include <linux/pwm.h>
52 unsigned int offset) in rcar_pwm_write() argument
54 writel(data, rp->base + offset); in rcar_pwm_write()
57 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) in rcar_pwm_read() argument
59 return readl(rp->base + offset); in rcar_pwm_read()
63 unsigned int offset) in rcar_pwm_update() argument
67 value = rcar_pwm_read(rp, offset); in rcar_pwm_update()
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| D | pwm-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pwm.h>
43 * The list of clocks required by PWM channels, and each channel has 2 clocks:
44 * enable clock and pwm clock.
55 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); in sprd_pwm_read() local
57 return readl_relaxed(spc->base + offset); in sprd_pwm_read()
63 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); in sprd_pwm_write() local
65 writel_relaxed(val, spc->base + offset); in sprd_pwm_write()
68 static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in sprd_pwm_get_state() argument
73 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
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| /kernel/linux/linux-6.6/drivers/pwm/ |
| D | pwm-stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pwm.h>
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable()
47 dev_err(chip->dev, "error reading PWM#%u control\n", in stmpe_24xx_pwm_enable()
48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
54 ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value); in stmpe_24xx_pwm_enable()
56 dev_err(chip->dev, "error writing PWM#%u control\n", in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
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| D | pwm-pxa.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-pxa.c
5 * simple driver for PWM (Pulse Width Modulator) controller
7 * 2008-02-13 initial version
10 * Links to reference manuals for some of the supported PWM chips can be found
14 * - When PWM is stopped, the current PWM period stops abruptly at the next
26 #include <linux/pwm.h>
34 /* PWM has_secondary_pwm? */
35 { "pxa25x-pwm", 0 },
36 { "pxa27x-pwm", HAS_SECONDARY_PWM },
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| D | pwm-lp3943.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI/National Semiconductor LP3943 PWM driver
15 #include <linux/pwm.h>
36 struct lp3943_platform_data *pdata = lp3943_pwm->pdata; in lp3943_pwm_request_map()
37 struct lp3943 *lp3943 = lp3943_pwm->lp3943; in lp3943_pwm_request_map()
39 int i, offset; in lp3943_pwm_request_map() local
43 return ERR_PTR(-ENOMEM); in lp3943_pwm_request_map()
45 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
46 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
48 for (i = 0; i < pwm_map->num_outputs; i++) { in lp3943_pwm_request_map()
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| D | pwm-atmel.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
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| D | pwm-pca9685.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for PCA9685 16-channel 12-bit PWM LED controller
8 * based on the pwm-twl-led.c driver
18 #include <linux/pwm.h>
28 * PWM channels requested afterwards must use a period that results in the same
97 /* No PWM enabled: Change allowed */ in pca9685_prescaler_can_change()
98 if (bitmap_empty(pca->pwms_enabled, PCA9685_MAXCHAN + 1)) in pca9685_prescaler_can_change()
100 /* More than one PWM enabled: Change not allowed */ in pca9685_prescaler_can_change()
101 if (bitmap_weight(pca->pwms_enabled, PCA9685_MAXCHAN + 1) > 1) in pca9685_prescaler_can_change()
104 * Only one PWM enabled: Change allowed if the PWM about to in pca9685_prescaler_can_change()
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| D | pwm-spear.c | 21 #include <linux/pwm.h>
27 /* PWM registers and bits definitions */
47 * struct spear_pwm_chip - struct representing pwm chip
49 * @mmio_base: base address of pwm chip
50 * @clk: pointer to clk structure of pwm chip
51 * @chip: linux pwm chip representation
65 unsigned long offset) in spear_pwm_readl() argument
67 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
71 unsigned int num, unsigned long offset, in spear_pwm_writel() argument
74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
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| D | pwm-keembay.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Keem Bay PWM driver
10 * - Upon disabling a channel, the currently running
22 #include <linux/pwm.h>
34 /* PWM Register offset */
72 u32 val, u32 offset) in keembay_pwm_update_bits() argument
74 u32 buff = readl(priv->base + offset); in keembay_pwm_update_bits()
77 writel(buff, priv->base + offset); in keembay_pwm_update_bits()
92 static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in keembay_pwm_get_state() argument
100 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_get_state()
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| D | pwm-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom BCM7038 PWM driver
19 #include <linux/pwm.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
61 unsigned int offset) in brcmstb_pwm_readl() argument
64 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
66 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
70 unsigned int offset) in brcmstb_pwm_writel() argument
73 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
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| D | pwm-tiehrpwm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * EHRPWM PWM driver
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
10 #include <linux/pwm.h>
122 static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset) in ehrpwm_read() argument
124 return readw(base + offset); in ehrpwm_read()
127 static inline void ehrpwm_write(void __iomem *base, unsigned int offset, in ehrpwm_write() argument
130 writew(value, base + offset); in ehrpwm_write()
133 static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, in ehrpwm_modify() argument
138 val = readw(base + offset); in ehrpwm_modify()
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| D | pwm-rcar.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car PWM Timer driver
8 * - The hardware cannot generate a 0% duty cycle.
21 #include <linux/pwm.h>
53 unsigned int offset) in rcar_pwm_write() argument
55 writel(data, rp->base + offset); in rcar_pwm_write()
58 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) in rcar_pwm_read() argument
60 return readl(rp->base + offset); in rcar_pwm_read()
64 unsigned int offset) in rcar_pwm_update() argument
68 value = rcar_pwm_read(rp, offset); in rcar_pwm_update()
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| D | pwm-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pwm.h>
44 * The list of clocks required by PWM channels, and each channel has 2 clocks:
45 * enable clock and pwm clock.
56 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); in sprd_pwm_read() local
58 return readl_relaxed(spc->base + offset); in sprd_pwm_read()
64 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); in sprd_pwm_write() local
66 writel_relaxed(val, spc->base + offset); in sprd_pwm_write()
69 static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in sprd_pwm_get_state() argument
74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | ssd1307fb.txt | 4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | gpio-mvebu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 - Andrew Lunn <andrew@lunn.ch>
16 - enum:
17 - marvell,armada-8k-gpio
18 - marvell,orion-gpio
20 - items:
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| /kernel/linux/linux-6.6/drivers/leds/ |
| D | leds-pca9532.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pca9532.c - 16-bit Led dimmer
18 #include <linux/leds-pca9532.h>
48 u8 pwm[2]; member
101 .name = "leds-pca953x",
109 /* We have two pwm/blinkers, but 16 possible leds to drive. Additionally,
110 * the clever Thecus people are using one pwm to drive the beeper. So,
111 * as a compromise we average one pwm to the values requested by all
114 static int pca9532_calcpwm(struct i2c_client *client, int pwm, int blink, in pca9532_calcpwm() argument
119 for (i = 0; i < data->chip_info->num_leds; i++) { in pca9532_calcpwm()
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| /kernel/linux/linux-5.10/drivers/leds/ |
| D | leds-pca9532.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pca9532.c - 16-bit Led dimmer
18 #include <linux/leds-pca9532.h>
49 u8 pwm[2]; member
103 .name = "leds-pca953x",
111 /* We have two pwm/blinkers, but 16 possible leds to drive. Additionally,
112 * the clever Thecus people are using one pwm to drive the beeper. So,
113 * as a compromise we average one pwm to the values requested by all
116 static int pca9532_calcpwm(struct i2c_client *client, int pwm, int blink, in pca9532_calcpwm() argument
121 for (i = 0; i < data->chip_info->num_leds; i++) { in pca9532_calcpwm()
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