| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.h | 181 bool SetFlags, CondARM32::Cond Cond);
184 bool SetFlags, CondARM32::Cond Cond);
187 bool SetFlags, CondARM32::Cond Cond);
190 bool SetFlags, CondARM32::Cond Cond);
192 void b(Label *L, CondARM32::Cond Cond);
197 bool SetFlags, CondARM32::Cond Cond);
203 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
205 void clz(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
207 void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
209 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
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| D | IceAssemblerARM32.cpp | 143 IValueT encodeCondition(CondARM32::Cond Cond) { in encodeCondition() argument
144 return static_cast<IValueT>(Cond); in encodeCondition()
794 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, in emitType01() argument
806 assert(CondARM32::isDefined(Cond)); in emitType01()
807 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitType01()
814 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
820 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, RuleChecks, InstName); in emitType01()
823 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
842 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
848 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
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| D | IceTargetLoweringARM32.h | 225 explicit CondWhenTrue(CondARM32::Cond T0,
226 CondARM32::Cond T1 = CondARM32::kNone)
231 CondARM32::Cond WhenTrue0;
232 CondARM32::Cond WhenTrue1;
278 CondARM32::Cond Cond = CondARM32::AL);
323 CondARM32::Cond);
325 CondARM32::Cond);
335 CondARM32::Cond Pred = CondARM32::AL) {
339 CondARM32::Cond Pred = CondARM32::AL) {
347 CondARM32::Cond Pred = CondARM32::AL) {
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.cpp | 118 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in AnalyzeBranch()
147 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in AnalyzeBranch()
166 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
189 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
193 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
197 if (!Cond.empty()) in InsertBranch()
198 Opc = (unsigned)Cond[0].getImm(); in InsertBranch()
201 if (Cond.empty()) // Unconditional branch in InsertBranch()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInfo.cpp | 98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
112 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
113 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
123 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
124 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
167 ArrayRef<MachineOperand> Cond, in InsertBranch() argument
169 if (Cond.empty()) { in InsertBranch()
177 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in InsertBranch()
179 if (Cond[0].getImm()) { in InsertBranch()
180 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[1]); in InsertBranch()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInfo.cpp | 99 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
113 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
114 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
124 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
125 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
171 ArrayRef<MachineOperand> Cond, in insertBranch() argument
176 if (Cond.empty()) { in insertBranch()
184 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
186 if (Cond[0].getImm()) { in insertBranch()
187 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
80 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
83 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
89 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
92 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
99 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
100 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
104 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
105 if (Cond[i].isReg()) in BuildCondBr()
106 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
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| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_select_main.cpp | 45 TyI1 Cond; in testSelect() local
48 setElement(Cond, j, Index() % 2); in testSelect()
52 Ty ResultLlc = select(Cond, Value1, Value2); in testSelect()
53 Ty ResultSz = Subzero_::select(Cond, Value1, Value2); in testSelect()
60 std::cout << vectAsString<TI1>(Cond) in testSelect()
81 v4si32 Cond; in testSelect() local
84 setElement(Cond, j, Index() % 2); in testSelect()
88 v4f32 ResultLlc = select(Cond, Value1, Value2); in testSelect()
89 v4f32 ResultSz = Subzero_::select(Cond, Value1, Value2); in testSelect()
96 std::cout << vectAsString<v4i1>(Cond) in testSelect()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_emulate_loops.c | 200 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, in try_unroll_loop()
201 loop->Cond->U.I.SrcReg[0].Index)){ in try_unroll_loop()
202 limit = &loop->Cond->U.I.SrcReg[0]; in try_unroll_loop()
203 counter = &loop->Cond->U.I.SrcReg[1]; in try_unroll_loop()
205 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, in try_unroll_loop()
206 loop->Cond->U.I.SrcReg[1].Index)){ in try_unroll_loop()
207 limit = &loop->Cond->U.I.SrcReg[1]; in try_unroll_loop()
208 counter = &loop->Cond->U.I.SrcReg[0]; in try_unroll_loop()
286 switch(loop->Cond->U.I.Opcode){ in try_unroll_loop()
310 rc_remove_instruction(loop->Cond); in try_unroll_loop()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaInstrInfo.cpp | 90 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
93 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
98 if (Cond.empty()) // Unconditional branch in InsertBranch()
101 if (isAlphaIntCondCode(Cond[0].getImm())) in InsertBranch()
103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
111 if (isAlphaIntCondCode(Cond[0].getImm())) in InsertBranch()
113 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
220 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/ |
| D | LibCallsShrinkWrap.cpp | 95 void shrinkWrapCI(CallInst *CI, Value *Cond);
138 Value *Cond = nullptr; in performCallDomainErrorOnly() local
149 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f); in performCallDomainErrorOnly()
160 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ, in performCallDomainErrorOnly()
169 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f); in performCallDomainErrorOnly()
177 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f); in performCallDomainErrorOnly()
183 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
190 Value *Cond = nullptr; in performCallRangeErrorOnly() local
208 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
215 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 189 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
223 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
244 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
245 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
277 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
281 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
285 if (Cond.empty()) { in InsertBranch()
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
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| /external/clang/test/SemaCXX/ |
| D | vector.cpp | 43 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, in conditional() argument
46 __typeof__(Cond? c16 : c16) *c16p1 = &c16; in conditional()
47 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; in conditional()
48 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; in conditional()
49 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; in conditional()
52 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; in conditional()
53 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; in conditional()
54 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; in conditional()
55 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; in conditional()
58 (void)(Cond? c16 : ll16); in conditional()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 193 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
221 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
222 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
242 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
243 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
275 ArrayRef<MachineOperand> Cond, in insertBranch() argument
280 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
285 if (Cond.empty()) { in insertBranch()
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 193 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
221 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
222 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
242 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
243 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
275 ArrayRef<MachineOperand> Cond, in InsertBranch() argument
279 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
283 if (Cond.empty()) { in InsertBranch()
288 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
289 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
159 Cond[0].setImm(CC); in ReverseBranchCondition()
178 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
213 Cond.clear(); in AnalyzeBranch()
237 if (Cond.empty()) { in AnalyzeBranch()
240 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
246 assert(Cond.size() == 1); in AnalyzeBranch()
254 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
157 Cond[0].setImm(CC); in ReverseBranchCondition()
176 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
211 Cond.clear(); in analyzeBranch()
235 if (Cond.empty()) { in analyzeBranch()
238 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
244 assert(Cond.size() == 1); in analyzeBranch()
252 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
134 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
160 Cond[0].setImm(CC); in reverseBranchCondition()
179 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
214 Cond.clear(); in analyzeBranch()
238 if (Cond.empty()) { in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
247 assert(Cond.size() == 1); in analyzeBranch()
255 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 161 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
190 if (!Cond.empty()) in analyzeBranch()
196 Cond.push_back(I->getOperand(1)); in analyzeBranch()
197 Cond.push_back(I->getOperand(2)); in analyzeBranch()
198 Cond.push_back(I->getOperand(3)); in analyzeBranch()
213 Cond.clear(); in analyzeBranch()
339 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
340 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
341 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
361 ArrayRef<MachineOperand> Cond, in insertBranch() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 184 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
189 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
190 Cond.push_back(LastInst.getOperand(0)); in parseCondBranch()
191 Cond.push_back(LastInst.getOperand(1)); in parseCondBranch()
216 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
219 Cond.clear(); in analyzeBranch()
265 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
272 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
317 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
323 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
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| /external/python/cpython2/Misc/ |
| D | valgrind-python.supp | 39 Memcheck:Cond
153 ### Memcheck:Cond
183 ### Memcheck:Cond
204 Memcheck:Cond
237 Memcheck:Cond
247 Memcheck:Cond
268 Memcheck:Cond
292 ### Memcheck:Cond
303 ### Memcheck:Cond
318 Memcheck:Cond
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 262 SmallVectorImpl<MachineOperand>& Cond) { in AnalyzeCondBr() argument
269 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
272 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
278 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
323 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); in AnalyzeBranch()
349 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); in AnalyzeBranch()
357 const SmallVectorImpl<MachineOperand>& Cond) in BuildCondBr()
359 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
363 for (unsigned i = 1; i < Cond.size(); ++i) in BuildCondBr()
364 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
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| /external/python/cpython3/Misc/ |
| D | valgrind-python.supp | 39 Memcheck:Cond
153 ### Memcheck:Cond
183 ### Memcheck:Cond
204 Memcheck:Cond
237 Memcheck:Cond
247 Memcheck:Cond
268 Memcheck:Cond
292 ### Memcheck:Cond
303 ### Memcheck:Cond
317 Memcheck:Cond
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 82 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
89 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
92 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
101 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
108 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
109 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
113 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
114 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
116 MIB.add(Cond[i]); in BuildCondBr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 99 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
117 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
135 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
184 ArrayRef<MachineOperand> Cond, in insertBranch() argument
191 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
196 if (Cond.empty()) // Unconditional branch in insertBranch()
199 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in insertBranch()
205 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in insertBranch()
|